gpu: nvgpu: ACR code refactor

-Created struct nvgpu_acr to hold acr module related member
 within single struct which are currently spread across multiple structs
 like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
 using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr	to perform ACR specific operation,
 currently ACR ops were part PMU which caused to have always dependence
 on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
 gk20a_remove_support() method, earlier acr cleanup was part of
 pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
 statically for chip currently in execution & assign ops to point to
 needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
 function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
 based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
 HAL for all chips to bootstrap ACR, earlier had 3 different function for
 gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.

JIRA NVGPU-1148

Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
index b17028e7..f1cad65a 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
@@ -23,14 +23,10 @@
 #ifndef NVGPU_SEC2_GP106_H
 #define NVGPU_SEC2_GP106_H
 
-int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
-        unsigned int timeout);
-int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
-int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
-        void *desc, u32 bl_sz);
-void init_pmu_setup_hw1(struct gk20a *g);
-int init_sec2_setup_hw1(struct gk20a *g,
-                void *desc, u32 bl_sz);
 int gp106_sec2_reset(struct gk20a *g);
 
+int gp106_sec2_setup_hw_and_bl_bootstrap(struct gk20a *g,
+        struct hs_acr *acr_desc,
+        struct nvgpu_falcon_bl_info *bl_info);
+
 #endif /* NVGPU_SEC2_GP106_H */