gpu: nvgpu: falcon HAL to support SEC2

- Updated falcon controller HAL to support SEC2 falcon
& used "is_falcon_supported" flag to know the support on chip.
- Created falcon HAL “flcn_gp106.c/h” under gp106 to enable
support for SEC2 & inherited gk20a flcn support.
- Deleted SEC2 falcon related methods to make use of
generic flacon controller methods for SEC2.
- GP106 SEC2 code cleanup

NVPU JIRA-99

Change-Id: I846e8015ed33554b3d8a45795314f1d28eee482f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1510200
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 1 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.h b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
index e3da0abf..90dfc372 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.h
@@ -16,14 +16,11 @@
 
 int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
 int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout);
-void sec2_copy_to_dmem(struct nvgpu_pmu *pmu,
-                u32 dst, u8 *src, u32 size, u8 port);
-void sec2_dump_falcon_stats(struct nvgpu_pmu *pmu);
 int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
         void *desc, u32 bl_sz);
-void sec_enable_irq(struct nvgpu_pmu *pmu, bool enable);
 void init_pmu_setup_hw1(struct gk20a *g);
 int init_sec2_setup_hw1(struct gk20a *g,
                 void *desc, u32 bl_sz);
+int gp106_sec2_reset(struct gk20a *g);
 
 #endif /*__SEC2_H_*/