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authorAlex Waterman <alexw@nvidia.com>2017-03-15 19:42:12 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-06 21:14:48 -0400
commitb69020bff5dfa69cad926c9374cdbe9a62509ffd (patch)
tree222f6b6bc23561a38004a257cbac401e431ff3be /drivers/gpu/nvgpu/gp106/sec2_gp106.c
parentfa4ecf5730a75269e85cc41c2ad2ee61307e72a9 (diff)
gpu: nvgpu: Rename gk20a_mem_* functions
Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: Ibfdc1112d43f0a125e4487c250e3f977ffd2cd75 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323325 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/sec2_gp106.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index dd67f882..5a331480 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -170,7 +170,7 @@ int bl_bootstrap_sec2(struct pmu_gk20a *pmu,
170 pwr_pmu_new_instblk_ptr_f( 170 pwr_pmu_new_instblk_ptr_f(
171 gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | 171 gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
172 pwr_pmu_new_instblk_valid_f(1) | 172 pwr_pmu_new_instblk_valid_f(1) |
173 gk20a_aperture_mask(g, &mm->pmu.inst_block, 173 nvgpu_aperture_mask(g, &mm->pmu.inst_block,
174 pwr_pmu_new_instblk_target_sys_coh_f(), 174 pwr_pmu_new_instblk_target_sys_coh_f(),
175 pwr_pmu_new_instblk_target_fb_f())); 175 pwr_pmu_new_instblk_target_fb_f()));
176 176
@@ -315,7 +315,7 @@ void init_pmu_setup_hw1(struct gk20a *g)
315 pwr_pmu_new_instblk_ptr_f( 315 pwr_pmu_new_instblk_ptr_f(
316 gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | 316 gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
317 pwr_pmu_new_instblk_valid_f(1) | 317 pwr_pmu_new_instblk_valid_f(1) |
318 gk20a_aperture_mask(g, &mm->pmu.inst_block, 318 nvgpu_aperture_mask(g, &mm->pmu.inst_block,
319 pwr_pmu_new_instblk_target_sys_coh_f(), 319 pwr_pmu_new_instblk_target_sys_coh_f(),
320 pwr_pmu_new_instblk_target_fb_f())); 320 pwr_pmu_new_instblk_target_fb_f()));
321 321