gpu: nvgpu: Use nvgpu_timeout for all loops

There were still a few remaining loops where we did not use
nvgpu_timeout and required Tegra specific functions for detecting if
timeout should be skipped. Replace all of them with nvgpu_timeout and
remove including chip-id.h where possible.

FE power mode timeout loop also used wrong delay value. It always
waited for the whole max timeout instead of looping with smaller
increments.

If SEC2 ACR boot fails to halt, we should not try to check ACR result
from mailbox. Add an early return for that case.

JIRA NVGPU-16

Change-Id: I9f0984250d7d01785755338e39822e6631dcaa5a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323227

1 files changed, 20 insertions, 20 deletions

diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 0032bce7..dd67f882 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -35,10 +35,10 @@
 int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout)
 {
         u32 data = 0;
-        unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+        struct nvgpu_timeout to;
 
-        while (time_before(jiffies, end_jiffies) ||
-                        !tegra_platform_is_silicon()) {
+        nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER);
+        do {
                 gk20a_writel(g, psec_falcon_irqsclr_r(),
                              gk20a_readl(g, psec_falcon_irqsclr_r()) | (0x10));
                 data = gk20a_readl(g, psec_falcon_irqstat_r());
@@ -46,10 +46,10 @@ int sec2_clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout)
                         psec_falcon_irqstat_halt_true_f())
                         /*halt irq is clear*/
                         break;
-                timeout--;
                 udelay(1);
-        }
-        if (timeout == 0)
+        } while (!nvgpu_timeout_expired(&to));
+
+        if (nvgpu_timeout_peek_expired(&to))
                 return -EBUSY;
         return 0;
 }
@@ -58,10 +58,10 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
 {
         u32 data = 0;
         int completion = -EBUSY;
-        unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout);
+        struct nvgpu_timeout to;
 
-        while (time_before(jiffies, end_jiffies) ||
-                        !tegra_platform_is_silicon()) {
+        nvgpu_timeout_init(g, &to, timeout, NVGPU_TIMER_CPU_TIMER);
+        do {
                 data = gk20a_readl(g, psec_falcon_cpuctl_r());
                 if (data & psec_falcon_cpuctl_halt_intr_m()) {
                         /*CPU is halted break*/
@@ -69,21 +69,21 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
                         break;
                 }
                 udelay(1);
-        }
-        if (completion){
+        } while (!nvgpu_timeout_expired(&to));
+
+        if (completion) {
                 gk20a_err(dev_from_gk20a(g), "ACR boot timed out");
+                return completion;
         }
-        else {
 
-                g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r());
-                gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities);
-                data = gk20a_readl(g, psec_falcon_mailbox0_r());
-                if (data) {
+        g->acr.capabilities = gk20a_readl(g, psec_falcon_mailbox1_r());
+        gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities);
+        data = gk20a_readl(g, psec_falcon_mailbox0_r());
+        if (data) {
 
-                        gk20a_err(dev_from_gk20a(g),
-                                "ACR boot failed, err %x", data);
-                        completion = -EAGAIN;
-                }
+                gk20a_err(dev_from_gk20a(g),
+                        "ACR boot failed, err %x", data);
+                completion = -EAGAIN;
         }
 
         init_pmu_setup_hw1(g);