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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-06 15:09:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-07 16:48:24 -0400
commit86ecddf68734e4a938eda351f4dde11ab507de3f (patch)
tree3a8d89ace77fc3427da6243c81f224883954e8e9 /drivers/gpu/nvgpu/gp106/sec2_gp106.c
parentbb72b7e2ed215b26e1d9b94534c24ab4cfa52801 (diff)
gpu: nvgpu: gp106: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: I18955b4c46c082883ee0bf589ab17cd66ab0add2 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457346 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/sec2_gp106.c14
1 files changed, 5 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 5a331480..cc1e91f6 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -72,7 +72,7 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
72 } while (!nvgpu_timeout_expired(&to)); 72 } while (!nvgpu_timeout_expired(&to));
73 73
74 if (completion) { 74 if (completion) {
75 gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); 75 nvgpu_err(g, "ACR boot timed out");
76 return completion; 76 return completion;
77 } 77 }
78 78
@@ -81,8 +81,7 @@ int sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
81 data = gk20a_readl(g, psec_falcon_mailbox0_r()); 81 data = gk20a_readl(g, psec_falcon_mailbox0_r());
82 if (data) { 82 if (data) {
83 83
84 gk20a_err(dev_from_gk20a(g), 84 nvgpu_err(g, "ACR boot failed, err %x", data);
85 "ACR boot failed, err %x", data);
86 completion = -EAGAIN; 85 completion = -EAGAIN;
87 } 86 }
88 87
@@ -100,14 +99,12 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
100 u32 *src_u32 = (u32*)src; 99 u32 *src_u32 = (u32*)src;
101 100
102 if (size == 0) { 101 if (size == 0) {
103 gk20a_err(dev_from_gk20a(g), 102 nvgpu_err(g, "size is zero");
104 "size is zero");
105 return; 103 return;
106 } 104 }
107 105
108 if (dst & 0x3) { 106 if (dst & 0x3) {
109 gk20a_err(dev_from_gk20a(g), 107 nvgpu_err(g, "dst (0x%08x) not 4-byte aligned", dst);
110 "dst (0x%08x) not 4-byte aligned", dst);
111 return; 108 return;
112 } 109 }
113 110
@@ -137,8 +134,7 @@ void sec2_copy_to_dmem(struct pmu_gk20a *pmu,
137 data = gk20a_readl(g, psec_falcon_dmemc_r(port)) & addr_mask; 134 data = gk20a_readl(g, psec_falcon_dmemc_r(port)) & addr_mask;
138 size = ALIGN(size, 4); 135 size = ALIGN(size, 4);
139 if (data != dst + size) { 136 if (data != dst + size) {
140 gk20a_err(dev_from_gk20a(g), 137 nvgpu_err(g, "copy failed. bytes written %d, expected %d",
141 "copy failed. bytes written %d, expected %d",
142 data - dst, size); 138 data - dst, size);
143 } 139 }
144 nvgpu_mutex_release(&pmu->pmu_copy_lock); 140 nvgpu_mutex_release(&pmu->pmu_copy_lock);