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authorDebarshi Dutta <ddutta@nvidia.com>2018-08-22 00:27:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-29 20:46:51 -0400
commit74639b444251d7adc222400625eb59a3d53d0c0a (patch)
tree19373fbe8ee522863c990fdfa0db24e6474f5167 /drivers/gpu/nvgpu/gp106/sec2_gp106.c
parente3710e5431d8f14f1b8c2812f5c1aeeb7bdaac1c (diff)
gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL
In nvgpu repository, we have multiple accesses to methods in pmu_gk20a.h which have register accesses. Instead of directly invoking these methods, these are now called via HALs. Some common methods such as pmu_wait_message_cond which donot have any register accesses are moved to pmu_ipc.c and the method declarations are moved to pmu.h. Also, changed gm20b_pmu_dbg to nvgpu_dbg_pmu all across the code base. This would remove all indirect dependencies via gk20a.h into pmu_gk20a.h. As a result pmu_gk20a.h is now removed from gk20a.h JIRA-597 Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080 Signed-off-by: Debarshi Dutta <ddutta@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1804283 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/sec2_gp106.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 61424bfe..dec35a91 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -32,10 +32,6 @@
32#include <nvgpu/hw/gp106/hw_pwr_gp106.h> 32#include <nvgpu/hw/gp106/hw_pwr_gp106.h>
33#include <nvgpu/hw/gp106/hw_psec_gp106.h> 33#include <nvgpu/hw/gp106/hw_psec_gp106.h>
34 34
35/*Defines*/
36#define gm20b_dbg_pmu(g, fmt, arg...) \
37 nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
38
39int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, 35int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g,
40 unsigned int timeout) 36 unsigned int timeout)
41{ 37{
@@ -61,7 +57,7 @@ int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout)
61 57
62 g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, 58 g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn,
63 FALCON_MAILBOX_1); 59 FALCON_MAILBOX_1);
64 gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities); 60 nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities);
65 data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); 61 data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0);
66 if (data) { 62 if (data) {
67 nvgpu_err(g, "ACR boot failed, err %x", data); 63 nvgpu_err(g, "ACR boot failed, err %x", data);