diff options
author | Alex Waterman <alexw@nvidia.com> | 2018-02-28 12:19:19 -0500 |
---|---|---|
committer | Srikar Srimath Tirumala <srikars@nvidia.com> | 2018-02-28 16:49:22 -0500 |
commit | 5a35a95654d561fce09a3b9abf6b82bb7a29d74b (patch) | |
tree | 119a07134188d8e06c29a570dd8c6b143f39c9e1 /drivers/gpu/nvgpu/gp106/sec2_gp106.c | |
parent | 3fdd8e38b280123fd13bcc4f3fd8928c15e94db6 (diff) |
Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working"
Also revert other changes related to IO coherence. This may be the
culprit in a recent dev-kernel lockdown.
Bug 2070609
Change-Id: Ida178aef161fadbc6db9512521ea51c702c1564b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665914
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/sec2_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 8e4e5900..29aceb7c 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -99,7 +99,6 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, | |||
99 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 99 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
100 | pwr_pmu_new_instblk_valid_f(1) | | 100 | pwr_pmu_new_instblk_valid_f(1) | |
101 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | 101 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, |
102 | pwr_pmu_new_instblk_target_sys_ncoh_f(), | ||
103 | pwr_pmu_new_instblk_target_sys_coh_f(), | 102 | pwr_pmu_new_instblk_target_sys_coh_f(), |
104 | pwr_pmu_new_instblk_target_fb_f())); | 103 | pwr_pmu_new_instblk_target_fb_f())); |
105 | 104 | ||
@@ -166,7 +165,6 @@ void init_pmu_setup_hw1(struct gk20a *g) | |||
166 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | 165 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
167 | pwr_pmu_new_instblk_valid_f(1) | | 166 | pwr_pmu_new_instblk_valid_f(1) | |
168 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | 167 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, |
169 | pwr_pmu_new_instblk_target_sys_ncoh_f(), | ||
170 | pwr_pmu_new_instblk_target_sys_coh_f(), | 168 | pwr_pmu_new_instblk_target_sys_coh_f(), |
171 | pwr_pmu_new_instblk_target_fb_f())); | 169 | pwr_pmu_new_instblk_target_fb_f())); |
172 | 170 | ||