gpu: nvgpu: Cleanup generic MM code in gk20a/mm_gk20a.c

Move much of the remaining generic MM code to a new common location:
common/mm/mm.c. Also add a corresponding <nvgpu/mm.h> header. This
mostly consists of init and cleanup code to handle the common MM
data structures like the VIDMEM code, address spaces for various
engines, etc.

A few more indepth changes were made as well.

1. alloc_inst_block() has been added to the MM HAL. This used to be
   defined directly in the gk20a code but it used a register. As a
   result, if this register hypothetically changes in the future,
   it would need to become a HAL anyway. This path preempts that
   and for now just defines all HALs to use the gk20a version.

2. Rename as much as possible: global functions are, for the most
   part, prepended with nvgpu (there are a few exceptions which I
   have yet to decide what to do with). Functions that are static
   are renamed to be as consistent with their functionality as
   possible since in some cases function effect and function name
   have diverged.

JIRA NVGPU-30

Change-Id: Ic948f1ecc2f7976eba4bb7169a44b7226bb7c0b5
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1574499
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
index 9f0fe375..26ded39e 100644
--- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c
@@ -22,6 +22,7 @@
 
 #include <nvgpu/pmu.h>
 #include <nvgpu/falcon.h>
+#include <nvgpu/mm.h>
 
 #include "gk20a/gk20a.h"
 #include "sec2_gp106.h"
@@ -88,7 +89,7 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu,
 
         gk20a_writel(g, psec_falcon_nxtctx_r(),
                         pwr_pmu_new_instblk_ptr_f(
-                        gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+                        nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
                         pwr_pmu_new_instblk_valid_f(1) |
                         nvgpu_aperture_mask(g, &mm->pmu.inst_block,
                                 pwr_pmu_new_instblk_target_sys_coh_f(),
@@ -154,7 +155,7 @@ void init_pmu_setup_hw1(struct gk20a *g)
                                 pwr_falcon_itfen_ctxen_enable_f());
         gk20a_writel(g, pwr_pmu_new_instblk_r(),
                                 pwr_pmu_new_instblk_ptr_f(
-                                        gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
+                                        nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) |
                                 pwr_pmu_new_instblk_valid_f(1) |
                                 nvgpu_aperture_mask(g, &mm->pmu.inst_block,
                                         pwr_pmu_new_instblk_target_sys_coh_f(),