gpu: nvgpu: resolve MISRA 10.3 violations

MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.

This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.

JIRA NVGPU-647

Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 12 insertions, 12 deletions

diff --git a/drivers/gpu/nvgpu/gp106/regops_gp106.c b/drivers/gpu/nvgpu/gp106/regops_gp106.c
index d9dadbac..25b88eeb 100644
--- a/drivers/gpu/nvgpu/gp106/regops_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/regops_gp106.c
@@ -1,7 +1,7 @@
 /*
  * Tegra GP106 GPU Debugger Driver Register Ops
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -1686,7 +1686,7 @@ static const struct regop_offset_range gp106_global_whitelist_ranges[] = {
 };
 
 
-static const u32 gp106_global_whitelist_ranges_count =
+static const u64 gp106_global_whitelist_ranges_count =
         ARRAY_SIZE(gp106_global_whitelist_ranges);
 
 /* context */
@@ -1694,24 +1694,24 @@ static const u32 gp106_global_whitelist_ranges_count =
 /* runcontrol */
 static const u32 gp106_runcontrol_whitelist[] = {
 };
-static const u32 gp106_runcontrol_whitelist_count =
+static const u64 gp106_runcontrol_whitelist_count =
         ARRAY_SIZE(gp106_runcontrol_whitelist);
 
 static const struct regop_offset_range gp106_runcontrol_whitelist_ranges[] = {
 };
-static const u32 gp106_runcontrol_whitelist_ranges_count =
+static const u64 gp106_runcontrol_whitelist_ranges_count =
         ARRAY_SIZE(gp106_runcontrol_whitelist_ranges);
 
 
 /* quad ctl */
 static const u32 gp106_qctl_whitelist[] = {
 };
-static const u32 gp106_qctl_whitelist_count =
+static const u64 gp106_qctl_whitelist_count =
         ARRAY_SIZE(gp106_qctl_whitelist);
 
 static const struct regop_offset_range gp106_qctl_whitelist_ranges[] = {
 };
-static const u32 gp106_qctl_whitelist_ranges_count =
+static const u64 gp106_qctl_whitelist_ranges_count =
         ARRAY_SIZE(gp106_qctl_whitelist_ranges);
 
 const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
@@ -1719,7 +1719,7 @@ const struct regop_offset_range *gp106_get_global_whitelist_ranges(void)
         return gp106_global_whitelist_ranges;
 }
 
-int gp106_get_global_whitelist_ranges_count(void)
+u64 gp106_get_global_whitelist_ranges_count(void)
 {
         return gp106_global_whitelist_ranges_count;
 }
@@ -1729,7 +1729,7 @@ const struct regop_offset_range *gp106_get_context_whitelist_ranges(void)
         return gp106_global_whitelist_ranges;
 }
 
-int gp106_get_context_whitelist_ranges_count(void)
+u64 gp106_get_context_whitelist_ranges_count(void)
 {
         return gp106_global_whitelist_ranges_count;
 }
@@ -1739,7 +1739,7 @@ const u32 *gp106_get_runcontrol_whitelist(void)
         return gp106_runcontrol_whitelist;
 }
 
-int gp106_get_runcontrol_whitelist_count(void)
+u64 gp106_get_runcontrol_whitelist_count(void)
 {
         return gp106_runcontrol_whitelist_count;
 }
@@ -1749,7 +1749,7 @@ const struct regop_offset_range *gp106_get_runcontrol_whitelist_ranges(void)
         return gp106_runcontrol_whitelist_ranges;
 }
 
-int gp106_get_runcontrol_whitelist_ranges_count(void)
+u64 gp106_get_runcontrol_whitelist_ranges_count(void)
 {
         return gp106_runcontrol_whitelist_ranges_count;
 }
@@ -1759,7 +1759,7 @@ const u32 *gp106_get_qctl_whitelist(void)
         return gp106_qctl_whitelist;
 }
 
-int gp106_get_qctl_whitelist_count(void)
+u64 gp106_get_qctl_whitelist_count(void)
 {
         return gp106_qctl_whitelist_count;
 }
@@ -1769,7 +1769,7 @@ const struct regop_offset_range *gp106_get_qctl_whitelist_ranges(void)
         return gp106_qctl_whitelist_ranges;
 }
 
-int gp106_get_qctl_whitelist_ranges_count(void)
+u64 gp106_get_qctl_whitelist_ranges_count(void)
 {
         return gp106_qctl_whitelist_ranges_count;
 }