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authorsmadhavan <smadhavan@nvidia.com>2018-09-11 01:46:21 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-14 02:45:19 -0400
commit852d77ffafdb8726a8e3cb1cc45cb63b90cb4c3c (patch)
tree7fe0876cce51b86f037661fb04234e2f06acd6ba /drivers/gpu/nvgpu/gp106/pmu_gp106.h
parent1d9d7c04bbbaa38080c3c8f256546bd63f65d494 (diff)
nvgpu: gp106: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in gp106 by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I2a2d94dd04f4ed7307b7579fccb9d23154cb4946 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1808250 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/pmu_gp106.h')
-rw-r--r--drivers/gpu/nvgpu/gp106/pmu_gp106.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
index 361f6e8b..9cf1202e 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h
@@ -20,8 +20,8 @@
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21 */ 21 */
22 22
23#ifndef __PMU_GP106_H_ 23#ifndef NVGPU_PMU_GP106_H
24#define __PMU_GP106_H_ 24#define NVGPU_PMU_GP106_H
25 25
26#define gp106_dbg_pmu(g, fmt, arg...) \ 26#define gp106_dbg_pmu(g, fmt, arg...) \
27 nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) 27 nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
@@ -42,4 +42,4 @@ void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
42bool gp106_pmu_is_engine_in_reset(struct gk20a *g); 42bool gp106_pmu_is_engine_in_reset(struct gk20a *g);
43int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset); 43int gp106_pmu_engine_reset(struct gk20a *g, bool do_reset);
44 44
45#endif /*__PMU_GP106_H_*/ 45#endif /* NVGPU_PMU_GP106_H */