gpu: nvgpu: Remove PMU gm204/gm206 support

-Created new methods for PMU gp106 whichever dependent
on gm206.
-Deleted pmu_gm206.c/h files & removed its involvement
from dependent files.

Change-Id: Ic578da53bff362efb3e142962275227787206233
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1304492
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 106 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index 9aac5328..5a9d5ba6 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -17,7 +17,6 @@
 #include "gk20a/pmu_gk20a.h"
 
 #include "gm20b/pmu_gm20b.h"
-#include "gm206/pmu_gm206.h"
 #include "gp10b/pmu_gp10b.h"
 #include "gp106/pmu_gp106.h"
 #include "gp106/acr_gp106.h"
@@ -299,6 +298,109 @@ static bool gp106_pmu_is_lpwr_feature_supported(struct gk20a *g, u32 feature_id)
         return is_feature_supported;
 }
 
+static bool gp106_is_lazy_bootstrap(u32 falcon_id)
+{
+        bool enable_status = false;
+
+        switch (falcon_id) {
+        case LSF_FALCON_ID_FECS:
+                enable_status = true;
+                break;
+        case LSF_FALCON_ID_GPCCS:
+                enable_status = true;
+                break;
+        default:
+                break;
+        }
+
+        return enable_status;
+}
+
+static bool gp106_is_priv_load(u32 falcon_id)
+{
+        bool enable_status = false;
+
+        switch (falcon_id) {
+        case LSF_FALCON_ID_FECS:
+                enable_status = true;
+                break;
+        case LSF_FALCON_ID_GPCCS:
+                enable_status = true;
+                break;
+        default:
+                break;
+        }
+
+        return enable_status;
+}
+
+static void gp106_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask,
+                                         u32 flags)
+{
+        struct pmu_gk20a *pmu = &g->pmu;
+        struct pmu_cmd cmd;
+        u32 seq;
+
+        gk20a_dbg_fn("");
+
+        gp106_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone);
+        if (g->ops.pmu.lspmuwprinitdone) {
+                /* send message to load FECS falcon */
+                memset(&cmd, 0, sizeof(struct pmu_cmd));
+                cmd.hdr.unit_id = PMU_UNIT_ACR;
+                cmd.hdr.size = PMU_CMD_HDR_SIZE +
+                  sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons);
+                cmd.cmd.acr.boot_falcons.cmd_type =
+                  PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS;
+                cmd.cmd.acr.boot_falcons.flags = flags;
+                cmd.cmd.acr.boot_falcons.falconidmask =
+                                falconidmask;
+                cmd.cmd.acr.boot_falcons.usevamask = 0;
+                cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = 0;
+                cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = 0;
+
+                gp106_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n",
+                                falconidmask);
+                gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                                pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
+        }
+
+        gk20a_dbg_fn("done");
+}
+
+static int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
+{
+        u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
+
+        /* GM20B PMU supports loading FECS and GPCCS only */
+        if (falconidmask == 0)
+                return -EINVAL;
+        if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) |
+                        (1 << LSF_FALCON_ID_GPCCS)))
+                return -EINVAL;
+        g->ops.pmu.lsfloadedfalconid = 0;
+        /* check whether pmu is ready to bootstrap lsf if not wait for it */
+        if (!g->ops.pmu.lspmuwprinitdone) {
+                pmu_wait_message_cond(&g->pmu,
+                                gk20a_get_gr_idle_timeout(g),
+                                &g->ops.pmu.lspmuwprinitdone, 1);
+                /* check again if it still not ready indicate an error */
+                if (!g->ops.pmu.lspmuwprinitdone) {
+                        gk20a_err(dev_from_gk20a(g),
+                                "PMU not ready to load LSF");
+                        return -ETIMEDOUT;
+                }
+        }
+        /* load falcon(s) */
+        gp106_pmu_load_multiple_falcons(g, falconidmask, flags);
+        pmu_wait_message_cond(&g->pmu,
+                        gk20a_get_gr_idle_timeout(g),
+                        &g->ops.pmu.lsfloadedfalconid, falconidmask);
+        if (g->ops.pmu.lsfloadedfalconid != falconidmask)
+                return -ETIMEDOUT;
+        return 0;
+}
+
 void gp106_init_pmu_ops(struct gpu_ops *gops)
 {
         gk20a_dbg_fn("");
@@ -306,9 +408,9 @@ void gp106_init_pmu_ops(struct gpu_ops *gops)
         if (gops->privsecurity) {
                 gp106_init_secure_pmu(gops);
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
-                gops->pmu.load_lsfalcon_ucode = gm206_load_falcon_ucode;
-                gops->pmu.is_lazy_bootstrap = gm206_is_lazy_bootstrap;
-                gops->pmu.is_priv_load = gm206_is_priv_load;
+                gops->pmu.load_lsfalcon_ucode = gp106_load_falcon_ucode;
+                gops->pmu.is_lazy_bootstrap = gp106_is_lazy_bootstrap;
+                gops->pmu.is_priv_load = gp106_is_priv_load;
         } else {
                 gk20a_init_pmu_ops(gops);
                 gops->pmu.pmu_setup_hw_and_bootstrap =