diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-09-10 11:41:49 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-24 11:12:03 -0400 |
commit | 863b47064445b3dd5cdc354821c8d3d14deade33 (patch) | |
tree | 1e53f26c1549d1970d752f74ab82a4d55642620b /drivers/gpu/nvgpu/gp106/pmu_gp106.c | |
parent | fdf77eda18b59c305d4dd8436d8b09d42ec4718a (diff) |
gpu: nvgpu: PMU init sequence change
-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
for PMU RTOS & does start PMU RTOS in secure & non-secure
based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
secured_pmu_start assignment for gp106 & gv100 to support
modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
to handle non secure PMU bootstrap, reused this method
for need chips.
JIRA NVGPU-1146
Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/pmu_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 031ac7d8..3e4a7390 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -306,3 +306,61 @@ int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
306 | } | 306 | } |
307 | return 0; | 307 | return 0; |
308 | } | 308 | } |
309 | |||
310 | void gp106_update_lspmu_cmdline_args(struct gk20a *g) | ||
311 | { | ||
312 | struct nvgpu_pmu *pmu = &g->pmu; | ||
313 | |||
314 | /*Copying pmu cmdline args*/ | ||
315 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, 0); | ||
316 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | ||
317 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | ||
318 | pmu, GK20A_PMU_TRACE_BUFSIZE); | ||
319 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | ||
320 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | ||
321 | pmu, GK20A_PMU_DMAIDX_VIRT); | ||
322 | if (g->ops.pmu_ver.config_pmu_cmdline_args_super_surface) { | ||
323 | g->ops.pmu_ver.config_pmu_cmdline_args_super_surface(pmu); | ||
324 | } | ||
325 | |||
326 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | ||
327 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | ||
328 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | ||
329 | |||
330 | } | ||
331 | |||
332 | void gp106_pmu_setup_apertures(struct gk20a *g) | ||
333 | { | ||
334 | struct mm_gk20a *mm = &g->mm; | ||
335 | |||
336 | /* PMU TRANSCFG */ | ||
337 | /* setup apertures - virtual */ | ||
338 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
339 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
340 | pwr_fbif_transcfg_target_local_fb_f()); | ||
341 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
342 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
343 | /* setup apertures - physical */ | ||
344 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
345 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
346 | pwr_fbif_transcfg_target_local_fb_f()); | ||
347 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
348 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
349 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
350 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
351 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
352 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
353 | |||
354 | /* PMU Config */ | ||
355 | gk20a_writel(g, pwr_falcon_itfen_r(), | ||
356 | gk20a_readl(g, pwr_falcon_itfen_r()) | | ||
357 | pwr_falcon_itfen_ctxen_enable_f()); | ||
358 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | ||
359 | pwr_pmu_new_instblk_ptr_f( | ||
360 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | | ||
361 | pwr_pmu_new_instblk_valid_f(1) | | ||
362 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | ||
363 | pwr_pmu_new_instblk_target_sys_ncoh_f(), | ||
364 | pwr_pmu_new_instblk_target_sys_coh_f(), | ||
365 | pwr_pmu_new_instblk_target_fb_f())); | ||
366 | } | ||