gpu: nvgpu: gp106: MCLK P8/P5 sequences and API

Adds P5/P8 sequences and simple debugfs API to
change from P0->P5

JIRA DNVGPU-117

Change-Id: I5811a5bddd0e11074524cce421bff1e3d441228d
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1208655
(cherry picked from commit dd410a86263e2407e043743945cf09a77910d745)
Reviewed-on: http://git-master/r/1231035
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index 48653142..f3e7b298 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -195,7 +195,7 @@ void gp106_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
         gops->pmu.dump_secure_fuses = NULL;
         gops->pmu.reset = gp106_falcon_reset;
-        gops->pmu.mclk_init = clk_mclkseq_build_prgm_gddr5;
+        gops->pmu.mclk_init = clk_mclkseq_init_mclk_gddr5;
 
         gk20a_dbg_fn("done");
 }