diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:01:00 -0500 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:35:06 -0500 |
commit | 7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch) | |
tree | 92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h | |
parent | 505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff) | |
parent | 2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff) |
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h | 553 |
1 files changed, 553 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h new file mode 100644 index 00000000..d760b588 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/hw_ltc_gp106.h | |||
@@ -0,0 +1,553 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ltc_gp106_h_ | ||
51 | #define _hw_ltc_gp106_h_ | ||
52 | |||
53 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | ||
54 | { | ||
55 | return 0x0014046c; | ||
56 | } | ||
57 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) | ||
58 | { | ||
59 | return 0x00140518; | ||
60 | } | ||
61 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) | ||
62 | { | ||
63 | return 0x0017e318; | ||
64 | } | ||
65 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) | ||
66 | { | ||
67 | return 0x1 << 15; | ||
68 | } | ||
69 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) | ||
70 | { | ||
71 | return 0x00140494; | ||
72 | } | ||
73 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) | ||
74 | { | ||
75 | return (r >> 0) & 0xffff; | ||
76 | } | ||
77 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) | ||
78 | { | ||
79 | return (r >> 16) & 0x3; | ||
80 | } | ||
81 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) | ||
82 | { | ||
83 | return 0x00000000; | ||
84 | } | ||
85 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) | ||
86 | { | ||
87 | return 0x00000001; | ||
88 | } | ||
89 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) | ||
90 | { | ||
91 | return 0x00000002; | ||
92 | } | ||
93 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) | ||
94 | { | ||
95 | return 0x0017e26c; | ||
96 | } | ||
97 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) | ||
98 | { | ||
99 | return 0x1; | ||
100 | } | ||
101 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) | ||
102 | { | ||
103 | return 0x2; | ||
104 | } | ||
105 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) | ||
106 | { | ||
107 | return (r >> 2) & 0x1; | ||
108 | } | ||
109 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) | ||
110 | { | ||
111 | return 0x00000001; | ||
112 | } | ||
113 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) | ||
114 | { | ||
115 | return 0x4; | ||
116 | } | ||
117 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) | ||
118 | { | ||
119 | return 0x0014046c; | ||
120 | } | ||
121 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | ||
122 | { | ||
123 | return 0x0017e270; | ||
124 | } | ||
125 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | ||
126 | { | ||
127 | return (v & 0x3ffff) << 0; | ||
128 | } | ||
129 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | ||
130 | { | ||
131 | return 0x0017e274; | ||
132 | } | ||
133 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) | ||
134 | { | ||
135 | return (v & 0x3ffff) << 0; | ||
136 | } | ||
137 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) | ||
138 | { | ||
139 | return 0x0003ffff; | ||
140 | } | ||
141 | static inline u32 ltc_ltcs_ltss_cbc_base_r(void) | ||
142 | { | ||
143 | return 0x0017e278; | ||
144 | } | ||
145 | static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) | ||
146 | { | ||
147 | return 0x0000000b; | ||
148 | } | ||
149 | static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) | ||
150 | { | ||
151 | return (r >> 0) & 0x3ffffff; | ||
152 | } | ||
153 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) | ||
154 | { | ||
155 | return 0x0017e27c; | ||
156 | } | ||
157 | static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) | ||
158 | { | ||
159 | return 0x0017e000; | ||
160 | } | ||
161 | static inline u32 ltc_ltcs_ltss_cbc_param_r(void) | ||
162 | { | ||
163 | return 0x0017e280; | ||
164 | } | ||
165 | static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) | ||
166 | { | ||
167 | return (r >> 0) & 0xffff; | ||
168 | } | ||
169 | static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) | ||
170 | { | ||
171 | return (r >> 24) & 0xf; | ||
172 | } | ||
173 | static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) | ||
174 | { | ||
175 | return (r >> 28) & 0xf; | ||
176 | } | ||
177 | static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) | ||
178 | { | ||
179 | return 0x0017e3f4; | ||
180 | } | ||
181 | static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) | ||
182 | { | ||
183 | return (r >> 0) & 0xffff; | ||
184 | } | ||
185 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) | ||
186 | { | ||
187 | return 0x0017e2ac; | ||
188 | } | ||
189 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) | ||
190 | { | ||
191 | return (v & 0x1f) << 16; | ||
192 | } | ||
193 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) | ||
194 | { | ||
195 | return 0x0017e338; | ||
196 | } | ||
197 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) | ||
198 | { | ||
199 | return (v & 0xf) << 0; | ||
200 | } | ||
201 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) | ||
202 | { | ||
203 | return 0x0017e33c + i*4; | ||
204 | } | ||
205 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) | ||
206 | { | ||
207 | return 0x00000004; | ||
208 | } | ||
209 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) | ||
210 | { | ||
211 | return 0x0017e34c; | ||
212 | } | ||
213 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) | ||
214 | { | ||
215 | return 32; | ||
216 | } | ||
217 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) | ||
218 | { | ||
219 | return (v & 0xffffffff) << 0; | ||
220 | } | ||
221 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) | ||
222 | { | ||
223 | return 0xffffffff << 0; | ||
224 | } | ||
225 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) | ||
226 | { | ||
227 | return (r >> 0) & 0xffffffff; | ||
228 | } | ||
229 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) | ||
230 | { | ||
231 | return 0x0017e2b0; | ||
232 | } | ||
233 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) | ||
234 | { | ||
235 | return 0x10000000; | ||
236 | } | ||
237 | static inline u32 ltc_ltcs_ltss_g_elpg_r(void) | ||
238 | { | ||
239 | return 0x0017e214; | ||
240 | } | ||
241 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) | ||
242 | { | ||
243 | return (r >> 0) & 0x1; | ||
244 | } | ||
245 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) | ||
246 | { | ||
247 | return 0x00000001; | ||
248 | } | ||
249 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) | ||
250 | { | ||
251 | return 0x1; | ||
252 | } | ||
253 | static inline u32 ltc_ltc0_ltss_g_elpg_r(void) | ||
254 | { | ||
255 | return 0x00140214; | ||
256 | } | ||
257 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) | ||
258 | { | ||
259 | return (r >> 0) & 0x1; | ||
260 | } | ||
261 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) | ||
262 | { | ||
263 | return 0x00000001; | ||
264 | } | ||
265 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) | ||
266 | { | ||
267 | return 0x1; | ||
268 | } | ||
269 | static inline u32 ltc_ltc1_ltss_g_elpg_r(void) | ||
270 | { | ||
271 | return 0x00142214; | ||
272 | } | ||
273 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) | ||
274 | { | ||
275 | return (r >> 0) & 0x1; | ||
276 | } | ||
277 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) | ||
278 | { | ||
279 | return 0x00000001; | ||
280 | } | ||
281 | static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) | ||
282 | { | ||
283 | return 0x1; | ||
284 | } | ||
285 | static inline u32 ltc_ltcs_ltss_intr_r(void) | ||
286 | { | ||
287 | return 0x0017e20c; | ||
288 | } | ||
289 | static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) | ||
290 | { | ||
291 | return 0x100; | ||
292 | } | ||
293 | static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) | ||
294 | { | ||
295 | return 0x200; | ||
296 | } | ||
297 | static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) | ||
298 | { | ||
299 | return 0x1 << 20; | ||
300 | } | ||
301 | static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) | ||
302 | { | ||
303 | return 0x1 << 30; | ||
304 | } | ||
305 | static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) | ||
306 | { | ||
307 | return 0x1000000; | ||
308 | } | ||
309 | static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) | ||
310 | { | ||
311 | return 0x2000000; | ||
312 | } | ||
313 | static inline u32 ltc_ltc0_lts0_intr_r(void) | ||
314 | { | ||
315 | return 0x0014040c; | ||
316 | } | ||
317 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) | ||
318 | { | ||
319 | return 0x0014051c; | ||
320 | } | ||
321 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) | ||
322 | { | ||
323 | return 0xff << 0; | ||
324 | } | ||
325 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) | ||
326 | { | ||
327 | return (r >> 0) & 0xff; | ||
328 | } | ||
329 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) | ||
330 | { | ||
331 | return 0xff << 16; | ||
332 | } | ||
333 | static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) | ||
334 | { | ||
335 | return (r >> 16) & 0xff; | ||
336 | } | ||
337 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) | ||
338 | { | ||
339 | return 0x0017e2a0; | ||
340 | } | ||
341 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
342 | { | ||
343 | return (r >> 0) & 0x1; | ||
344 | } | ||
345 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
346 | { | ||
347 | return 0x00000001; | ||
348 | } | ||
349 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
350 | { | ||
351 | return 0x1; | ||
352 | } | ||
353 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) | ||
354 | { | ||
355 | return (r >> 8) & 0xf; | ||
356 | } | ||
357 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) | ||
358 | { | ||
359 | return 0x00000003; | ||
360 | } | ||
361 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) | ||
362 | { | ||
363 | return 0x300; | ||
364 | } | ||
365 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) | ||
366 | { | ||
367 | return (r >> 28) & 0x1; | ||
368 | } | ||
369 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) | ||
370 | { | ||
371 | return 0x00000001; | ||
372 | } | ||
373 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) | ||
374 | { | ||
375 | return 0x10000000; | ||
376 | } | ||
377 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) | ||
378 | { | ||
379 | return (r >> 29) & 0x1; | ||
380 | } | ||
381 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) | ||
382 | { | ||
383 | return 0x00000001; | ||
384 | } | ||
385 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) | ||
386 | { | ||
387 | return 0x20000000; | ||
388 | } | ||
389 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) | ||
390 | { | ||
391 | return (r >> 30) & 0x1; | ||
392 | } | ||
393 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) | ||
394 | { | ||
395 | return 0x00000001; | ||
396 | } | ||
397 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) | ||
398 | { | ||
399 | return 0x40000000; | ||
400 | } | ||
401 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) | ||
402 | { | ||
403 | return 0x0017e2a4; | ||
404 | } | ||
405 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
406 | { | ||
407 | return (r >> 0) & 0x1; | ||
408 | } | ||
409 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
410 | { | ||
411 | return 0x00000001; | ||
412 | } | ||
413 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
414 | { | ||
415 | return 0x1; | ||
416 | } | ||
417 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) | ||
418 | { | ||
419 | return (r >> 8) & 0xf; | ||
420 | } | ||
421 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) | ||
422 | { | ||
423 | return 0x00000003; | ||
424 | } | ||
425 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) | ||
426 | { | ||
427 | return 0x300; | ||
428 | } | ||
429 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) | ||
430 | { | ||
431 | return (r >> 16) & 0x1; | ||
432 | } | ||
433 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) | ||
434 | { | ||
435 | return 0x00000001; | ||
436 | } | ||
437 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) | ||
438 | { | ||
439 | return 0x10000; | ||
440 | } | ||
441 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) | ||
442 | { | ||
443 | return (r >> 28) & 0x1; | ||
444 | } | ||
445 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) | ||
446 | { | ||
447 | return 0x00000001; | ||
448 | } | ||
449 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) | ||
450 | { | ||
451 | return 0x10000000; | ||
452 | } | ||
453 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) | ||
454 | { | ||
455 | return (r >> 29) & 0x1; | ||
456 | } | ||
457 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) | ||
458 | { | ||
459 | return 0x00000001; | ||
460 | } | ||
461 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) | ||
462 | { | ||
463 | return 0x20000000; | ||
464 | } | ||
465 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) | ||
466 | { | ||
467 | return (r >> 30) & 0x1; | ||
468 | } | ||
469 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) | ||
470 | { | ||
471 | return 0x00000001; | ||
472 | } | ||
473 | static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) | ||
474 | { | ||
475 | return 0x40000000; | ||
476 | } | ||
477 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) | ||
478 | { | ||
479 | return 0x001402a0; | ||
480 | } | ||
481 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
482 | { | ||
483 | return (r >> 0) & 0x1; | ||
484 | } | ||
485 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
486 | { | ||
487 | return 0x00000001; | ||
488 | } | ||
489 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
490 | { | ||
491 | return 0x1; | ||
492 | } | ||
493 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) | ||
494 | { | ||
495 | return 0x001402a4; | ||
496 | } | ||
497 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
498 | { | ||
499 | return (r >> 0) & 0x1; | ||
500 | } | ||
501 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
502 | { | ||
503 | return 0x00000001; | ||
504 | } | ||
505 | static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
506 | { | ||
507 | return 0x1; | ||
508 | } | ||
509 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) | ||
510 | { | ||
511 | return 0x001422a0; | ||
512 | } | ||
513 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) | ||
514 | { | ||
515 | return (r >> 0) & 0x1; | ||
516 | } | ||
517 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) | ||
518 | { | ||
519 | return 0x00000001; | ||
520 | } | ||
521 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) | ||
522 | { | ||
523 | return 0x1; | ||
524 | } | ||
525 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) | ||
526 | { | ||
527 | return 0x001422a4; | ||
528 | } | ||
529 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) | ||
530 | { | ||
531 | return (r >> 0) & 0x1; | ||
532 | } | ||
533 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) | ||
534 | { | ||
535 | return 0x00000001; | ||
536 | } | ||
537 | static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) | ||
538 | { | ||
539 | return 0x1; | ||
540 | } | ||
541 | static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) | ||
542 | { | ||
543 | return 0x0014058c; | ||
544 | } | ||
545 | static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) | ||
546 | { | ||
547 | return (r >> 0) & 0xffff; | ||
548 | } | ||
549 | static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) | ||
550 | { | ||
551 | return (r >> 16) & 0x1f; | ||
552 | } | ||
553 | #endif | ||