diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:01:00 -0500 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:35:06 -0500 |
commit | 7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch) | |
tree | 92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h | |
parent | 505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff) | |
parent | 2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff) |
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h | 125 |
1 files changed, 125 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h b/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h new file mode 100644 index 00000000..65146d39 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/hw_ccsr_gp106.h | |||
@@ -0,0 +1,125 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ccsr_gp106_h_ | ||
51 | #define _hw_ccsr_gp106_h_ | ||
52 | |||
53 | static inline u32 ccsr_channel_inst_r(u32 i) | ||
54 | { | ||
55 | return 0x00800000 + i*8; | ||
56 | } | ||
57 | static inline u32 ccsr_channel_inst__size_1_v(void) | ||
58 | { | ||
59 | return 0x00001000; | ||
60 | } | ||
61 | static inline u32 ccsr_channel_inst_ptr_f(u32 v) | ||
62 | { | ||
63 | return (v & 0xfffffff) << 0; | ||
64 | } | ||
65 | static inline u32 ccsr_channel_inst_target_vid_mem_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void) | ||
70 | { | ||
71 | return 0x20000000; | ||
72 | } | ||
73 | static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void) | ||
74 | { | ||
75 | return 0x30000000; | ||
76 | } | ||
77 | static inline u32 ccsr_channel_inst_bind_false_f(void) | ||
78 | { | ||
79 | return 0x0; | ||
80 | } | ||
81 | static inline u32 ccsr_channel_inst_bind_true_f(void) | ||
82 | { | ||
83 | return 0x80000000; | ||
84 | } | ||
85 | static inline u32 ccsr_channel_r(u32 i) | ||
86 | { | ||
87 | return 0x00800004 + i*8; | ||
88 | } | ||
89 | static inline u32 ccsr_channel__size_1_v(void) | ||
90 | { | ||
91 | return 0x00001000; | ||
92 | } | ||
93 | static inline u32 ccsr_channel_enable_v(u32 r) | ||
94 | { | ||
95 | return (r >> 0) & 0x1; | ||
96 | } | ||
97 | static inline u32 ccsr_channel_enable_set_f(u32 v) | ||
98 | { | ||
99 | return (v & 0x1) << 10; | ||
100 | } | ||
101 | static inline u32 ccsr_channel_enable_set_true_f(void) | ||
102 | { | ||
103 | return 0x400; | ||
104 | } | ||
105 | static inline u32 ccsr_channel_enable_clr_true_f(void) | ||
106 | { | ||
107 | return 0x800; | ||
108 | } | ||
109 | static inline u32 ccsr_channel_status_v(u32 r) | ||
110 | { | ||
111 | return (r >> 24) & 0xf; | ||
112 | } | ||
113 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
114 | { | ||
115 | return 0x00000002; | ||
116 | } | ||
117 | static inline u32 ccsr_channel_busy_v(u32 r) | ||
118 | { | ||
119 | return (r >> 28) & 0x1; | ||
120 | } | ||
121 | static inline u32 ccsr_channel_next_v(u32 r) | ||
122 | { | ||
123 | return (r >> 1) & 0x1; | ||
124 | } | ||
125 | #endif | ||