gpu: nvgpu: Implement gp10b variant of cbc_ctrl

Pascal has support for more comptags than Maxwell, but we were using
gm20b definitions for cbc_ctrl on all chips. Specifically field
clear_upper_bound is one bit wider in Pascal.

Implement gp10b version of cbc_ctrl and take that into use in Pascal
and Volta.

Bug 200381317

Change-Id: I7d3cb9e92498e08f8704f156e2afb34404ce587e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642574
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 68562955..7a57672e 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -236,7 +236,7 @@ static const struct gpu_ops gp106_ops = {
                 .init_cbc = NULL,
                 .init_fs_state = gm20b_ltc_init_fs_state,
                 .init_comptags = gp10b_ltc_init_comptags,
-                .cbc_ctrl = gm20b_ltc_cbc_ctrl,
+                .cbc_ctrl = gp10b_ltc_cbc_ctrl,
                 .isr = gp10b_ltc_isr,
                 .cbc_fix_config = NULL,
                 .flush = gm20b_flush_ltc,