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authorDeepak Nibade <dnibade@nvidia.com>2018-09-21 02:36:36 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-24 13:14:56 -0400
commite16843c2efdffa13c15cc0a014b2a5598cc2f4ec (patch)
tree2942e8a53e954ab30b564a3eb07efc8c10270e10 /drivers/gpu/nvgpu/gp106/hal_gp106.c
parent2a26075b8408b45d18920e3f4ca08a457b23a7e0 (diff)
gpu: nvgpu: read GPC mask from h/w
In gk20a_ctrl_ioctl_gpu_characteristics() we right now just calculate GPC mask in s/w and return to user space But this could give incorrect result as any GPC could be floorswept in h/w Add gops.fuse.fuse_status_opt_gpc() to read GPC floorsweep status from fuse Add gops.gr.get_gpc_mask() to get actual GPC mask from h/w Set these HALs only for dGPUs right now. Fuse register to read GPC mask is not yet supported in simulation and hence simulation boot fails These HALs will be set for iGPU once simulation issue is resolved Use gops.gr.get_gpc_mask() if it is defined in gk20a_ctrl_ioctl_gpu_characteristics() to send the actual GPC mask to user space Jira NVGPUT-132 Change-Id: I3b552de07883328fcfa41d4334ec0d777e04bdd3 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1822811 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 3a2fa71d..e8ad68c2 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -293,6 +293,7 @@ static const struct gpu_ops gp106_ops = {
293 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, 293 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
294 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, 294 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
295 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, 295 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
296 .get_gpc_mask = gr_gm20b_get_gpc_mask,
296 .alloc_obj_ctx = gk20a_alloc_obj_ctx, 297 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
297 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, 298 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
298 .get_zcull_info = gr_gk20a_get_zcull_info, 299 .get_zcull_info = gr_gk20a_get_zcull_info,
@@ -794,6 +795,7 @@ static const struct gpu_ops gp106_ops = {
794 .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, 795 .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio,
795 .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, 796 .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp,
796 .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, 797 .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp,
798 .fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc,
797 .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, 799 .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc,
798 .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, 800 .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc,
799 .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, 801 .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en,