gpu: nvgpu: Make LTC disabling common code

Refactor the sync_debugfs LTC HAL op so that the logic to enable
or disable LTC goes to common code nvgpu_ltc_sync_enabled() and
the LTC HAL set_enabled only performs the hardware register access.

Create a new common function nvgpu_init_ltc_support() to initialize
the LTC software variable, and move hardware initialization of LTC to
be called from it.

JIRA NVGPU-62

Change-Id: Ib1cf4f5b83ca3dac08407464ed56a732e0a33923
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1528262
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 38778da7..4a891a82 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -204,9 +204,7 @@ static const struct gpu_ops gp106_ops = {
                 .isr = gp10b_ltc_isr,
                 .cbc_fix_config = NULL,
                 .flush = gm20b_flush_ltc,
-#ifdef CONFIG_DEBUG_FS
-                .sync_debugfs = gp10b_ltc_sync_debugfs,
-#endif
+                .set_enabled = gp10b_ltc_set_enabled,
         },
         .ce2 = {
                 .isr_stall = gp10b_ce_isr,