gpu: nvgpu: gp106 SEC2 falcon code update

- Added prefix gp106_ to sec2_wait_for_halt()
  & sec2_clear_halt_interrupt_status() for gp106
  SEC2 HAL
- Made changes to gp106_sec2_wait_for_halt() to
  read SEC2 falcon mailbox using common falcon
  mailbox access functions.
- Add define for falcon mailbox
- These changes are done to reuse gp106 HAL's
  for GPU_NEXT.

Change-Id: Id32a7636d775b482684212ed4ef5d01c8ea65335
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1755618
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index a22350ce..9427d3bf 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -621,9 +621,9 @@ static const struct gpu_ops gp106_ops = {
                 .alloc_blob_space = gp106_alloc_blob_space,
                 .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg,
                 .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc,
-                .falcon_wait_for_halt = sec2_wait_for_halt,
+                .falcon_wait_for_halt = gp106_sec2_wait_for_halt,
                 .falcon_clear_halt_interrupt_status =
-                        sec2_clear_halt_interrupt_status,
+                        gp106_sec2_clear_halt_interrupt_status,
                 .init_falcon_setup_hw = init_sec2_setup_hw1,
                 .pmu_queue_tail = gk20a_pmu_queue_tail,
                 .pmu_get_queue_head = pwr_pmu_queue_head_r,