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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-08-26 13:19:14 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:19 -0500
commit6d4851e248f00a0c8188bcaa1375f94ba915f608 (patch)
treefdc680c7d9142a3f3066324f31de35c1ced38b9c /drivers/gpu/nvgpu/gp106/hal_gp106.c
parenta74a971f498084bf9131be3964c380c74e9d5960 (diff)
gpu: nvgpu: gp106: Remove clock gating prod vals
We are using gp10b prod values for gp106, and they are incompatible. Because of this we are accessing invalid registers. Delete all prod vals for gp106 until we have generated new ones. Bug 1799537 Change-Id: Id805e933bd19f6ccaf28274cd69140f9f93cd4ea Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1208716 (cherry picked from commit 50d3ecfbfa42795d5eaa20c977cf83613498a804) Reviewed-on: http://git-master/r/1217287 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c51
1 files changed, 1 insertions, 50 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index eadeb1b4..5414eb4a 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -49,56 +49,7 @@
49#include "gk20a/css_gr_gk20a.h" 49#include "gk20a/css_gr_gk20a.h"
50 50
51static struct gpu_ops gp106_ops = { 51static struct gpu_ops gp106_ops = {
52 .clock_gating = { 52 .clock_gating = { }
53 .slcg_bus_load_gating_prod =
54 gp10b_slcg_bus_load_gating_prod,
55 .slcg_ce2_load_gating_prod =
56 gp10b_slcg_ce2_load_gating_prod,
57 .slcg_chiplet_load_gating_prod =
58 gp10b_slcg_chiplet_load_gating_prod,
59 .slcg_ctxsw_firmware_load_gating_prod =
60 gp10b_slcg_ctxsw_firmware_load_gating_prod,
61 .slcg_fb_load_gating_prod =
62 gp10b_slcg_fb_load_gating_prod,
63 .slcg_fifo_load_gating_prod =
64 gp10b_slcg_fifo_load_gating_prod,
65 .slcg_gr_load_gating_prod =
66 gr_gp10b_slcg_gr_load_gating_prod,
67 .slcg_ltc_load_gating_prod =
68 ltc_gp10b_slcg_ltc_load_gating_prod,
69 .slcg_perf_load_gating_prod =
70 gp10b_slcg_perf_load_gating_prod,
71 .slcg_priring_load_gating_prod =
72 gp10b_slcg_priring_load_gating_prod,
73 .slcg_pmu_load_gating_prod =
74 gp10b_slcg_pmu_load_gating_prod,
75 .slcg_therm_load_gating_prod =
76 gp10b_slcg_therm_load_gating_prod,
77 .slcg_xbar_load_gating_prod =
78 gp10b_slcg_xbar_load_gating_prod,
79 .blcg_bus_load_gating_prod =
80 gp10b_blcg_bus_load_gating_prod,
81 .blcg_ce_load_gating_prod =
82 gp10b_blcg_ce_load_gating_prod,
83 .blcg_ctxsw_firmware_load_gating_prod =
84 gp10b_blcg_ctxsw_firmware_load_gating_prod,
85 .blcg_fb_load_gating_prod =
86 gp10b_blcg_fb_load_gating_prod,
87 .blcg_fifo_load_gating_prod =
88 gp10b_blcg_fifo_load_gating_prod,
89 .blcg_gr_load_gating_prod =
90 gp10b_blcg_gr_load_gating_prod,
91 .blcg_ltc_load_gating_prod =
92 gp10b_blcg_ltc_load_gating_prod,
93 .blcg_pwr_csb_load_gating_prod =
94 gp10b_blcg_pwr_csb_load_gating_prod,
95 .blcg_pmu_load_gating_prod =
96 gp10b_blcg_pmu_load_gating_prod,
97 .blcg_xbar_load_gating_prod =
98 gp10b_blcg_xbar_load_gating_prod,
99 .pg_gr_load_gating_prod =
100 gr_gp10b_pg_gr_load_gating_prod,
101 }
102}; 53};
103 54
104static int gp106_get_litter_value(struct gk20a *g, 55static int gp106_get_litter_value(struct gk20a *g,