gpu: nvgpu: ACR code refactor

-Created struct nvgpu_acr to hold acr module related member
 within single struct which are currently spread across multiple structs
 like nvgpu_pmu, pmu_ops & gk20a.
-Created struct hs_flcn_bl struct to hold ACR HS bootloader specific members
-Created struct hs_acr to hold ACR ucode specific members like bootloader data
 using struct hs_flcn_bl, acr type & falcon info on which ACR ucode need to run.
-Created acr ops under struct nvgpu_acr	to perform ACR specific operation,
 currently ACR ops were part PMU which caused to have always dependence
 on PMU even though ACR was not executing on PMU.
-Added acr_remove_support ops which will be called as part of
 gk20a_remove_support() method, earlier acr cleanup was part of
 pmu remove_support method.
-Created define for ACR types,
-Ops acr_sw_init() function helps to set ACR properties
 statically for chip currently in execution & assign ops to point to
 needed functions as per chip.
-Ops acr_sw_init execute at early as nvgpu_init_mm_support calls acr
 function to alloc blob space.
-Created ops to fill bootloader descriptor & to patch WPR info to ACR uocde
 based on interfaces used to bootstrap ACR ucode.
-Created function gm20b_bootstrap_hs_acr() function which is now common
 HAL for all chips to bootstrap ACR, earlier had 3 different function for
 gm20b/gp10b, gv11b & for all dgpu based on interface needed.
-Removed duplicate code for falcon engine wherever common falcon code can be used.
-Removed ACR code dependent on PMU & made changes to use from nvgpu_acr.

JIRA NVGPU-1148

Change-Id: I39951d2fc9a0bb7ee6057e0fa06da78045d47590
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1813231
GVS: Gerrit_Virtual_Submit
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index e94bc1ea..048c0a45 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -800,6 +800,9 @@ static const struct gpu_ops gp106_ops = {
                 .read_vin_cal_gain_offset_fuse =
                         gp106_fuse_read_vin_cal_gain_offset_fuse,
         },
+        .acr = {
+                .acr_sw_init = nvgpu_gp106_acr_sw_init,
+        },
         .get_litter_value = gp106_get_litter_value,
         .chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
 };
@@ -855,6 +858,7 @@ int gp106_init_hal(struct gk20a *g)
         gops->falcon = gp106_ops.falcon;
         gops->priv_ring = gp106_ops.priv_ring;
         gops->fuse = gp106_ops.fuse;
+        gops->acr = gp106_ops.acr;
 
         /* Lone functions */
         gops->get_litter_value = gp106_ops.get_litter_value;
@@ -875,7 +879,6 @@ int gp106_init_hal(struct gk20a *g)
         }
 
         g->pmu_lsf_pmu_wpr_init_done = 0;
-        g->bootstrap_owner = LSF_FALCON_ID_SEC2;
         gops->clk.split_rail_support = true;
         gops->clk.support_clk_freq_controller = true;
         gops->clk.support_pmgr_domain = true;