diff options
author | Debarshi Dutta <ddutta@nvidia.com> | 2018-06-26 06:11:12 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-04 10:25:41 -0400 |
commit | 16ad9f537979c5f3717fc5781b1c2fad22a76f96 (patch) | |
tree | 2a150c50983180051fa5ecc942764e081961d787 /drivers/gpu/nvgpu/gp106/hal_gp106.c | |
parent | f125d1b681c324d5d58abcc42fac1301e1faa921 (diff) |
gpu: nvgpu: move gp106 specific clk_arbiter code into HAL
Currently, clock arbiter code is extensively using dgpu specific
implementation. This patch restructures the clk_arbiter code and moves
gp106 specific code into HAL. Following changes are made in this patch
1) clk_domain_get_f_points is now invoked via HAL for gp106 i.e.
g->ops.clk.clk_domain_get_f_points.
2) moved nvgpu_clk_arb_change_vf_point and other related static
functions to clk_arb_gp106.c.
3) Instead of only checking if get_arbiter_clk_domain is empty, a
check for support_clk_freq_controller is also added. This is to enable
the clk_arbiter based on support from both the OS and the chips.
Bug 2061372
Change-Id: I65b0a4e02145a86fbbfb420ed591b1fa3c86f6dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774279
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/hal_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 78a3ea63..167bfaac 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -675,6 +675,7 @@ static const struct gpu_ops gp106_ops = { | |||
675 | .get_crystal_clk_hz = gp106_crystal_clk_hz, | 675 | .get_crystal_clk_hz = gp106_crystal_clk_hz, |
676 | .measure_freq = gp106_clk_measure_freq, | 676 | .measure_freq = gp106_clk_measure_freq, |
677 | .suspend_clk_support = gp106_suspend_clk_support, | 677 | .suspend_clk_support = gp106_suspend_clk_support, |
678 | .clk_domain_get_f_points = gp106_clk_domain_get_f_points, | ||
678 | .mclk_init = gp106_mclk_init, | 679 | .mclk_init = gp106_mclk_init, |
679 | .mclk_change = gp106_mclk_change, | 680 | .mclk_change = gp106_mclk_change, |
680 | .mclk_deinit = gp106_mclk_deinit, | 681 | .mclk_deinit = gp106_mclk_deinit, |
@@ -684,6 +685,9 @@ static const struct gpu_ops gp106_ops = { | |||
684 | .get_arbiter_clk_range = gp106_get_arbiter_clk_range, | 685 | .get_arbiter_clk_range = gp106_get_arbiter_clk_range, |
685 | .get_arbiter_clk_default = gp106_get_arbiter_clk_default, | 686 | .get_arbiter_clk_default = gp106_get_arbiter_clk_default, |
686 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | 687 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, |
688 | .arbiter_clk_init = gp106_init_clk_arbiter, | ||
689 | .clk_arb_run_arbiter_cb = gp106_clk_arb_run_arbiter_cb, | ||
690 | .clk_arb_cleanup = gp106_clk_arb_cleanup, | ||
687 | }, | 691 | }, |
688 | .regops = { | 692 | .regops = { |
689 | .exec_regops = exec_regops_gk20a, | 693 | .exec_regops = exec_regops_gk20a, |
@@ -849,6 +853,7 @@ int gp106_init_hal(struct gk20a *g) | |||
849 | gops->clk.mclk_init = gp106_ops.clk.mclk_init; | 853 | gops->clk.mclk_init = gp106_ops.clk.mclk_init; |
850 | gops->clk.mclk_change = gp106_ops.clk.mclk_change; | 854 | gops->clk.mclk_change = gp106_ops.clk.mclk_change; |
851 | gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit; | 855 | gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit; |
856 | gops->clk.clk_domain_get_f_points = gp106_ops.clk.clk_domain_get_f_points; | ||
852 | 857 | ||
853 | gops->clk_arb = gp106_ops.clk_arb; | 858 | gops->clk_arb = gp106_ops.clk_arb; |
854 | gops->regops = gp106_ops.regops; | 859 | gops->regops = gp106_ops.regops; |