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authorSrirangan <smadhavan@nvidia.com>2018-08-27 01:59:01 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-29 11:59:35 -0400
commite3710e5431d8f14f1b8c2812f5c1aeeb7bdaac1c (patch)
tree8a6498b12e10f6b391d3c5dd7c6ac7b340ca60b4 /drivers/gpu/nvgpu/gp106/gr_gp106.c
parent2f97e683feed3c3ba3c8722c4f6ab7466bcef0c0 (diff)
gpu: nvgpu: gp106: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I8493274995ed8de526902dd0ca0808b2972e28aa Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1796806 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.c15
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
index 233357c8..a3fd8912 100644
--- a/drivers/gpu/nvgpu/gp106/gr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -129,8 +129,9 @@ void gr_gp106_cb_size_default(struct gk20a *g)
129{ 129{
130 struct gr_gk20a *gr = &g->gr; 130 struct gr_gk20a *gr = &g->gr;
131 131
132 if (!gr->attrib_cb_default_size) 132 if (!gr->attrib_cb_default_size) {
133 gr->attrib_cb_default_size = 0x800; 133 gr->attrib_cb_default_size = 0x800;
134 }
134 gr->alpha_cb_default_size = 135 gr->alpha_cb_default_size =
135 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 136 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
136 gr->attrib_cb_gfxp_default_size = 137 gr->attrib_cb_gfxp_default_size =
@@ -147,20 +148,24 @@ int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,
147{ 148{
148 int err = 0; 149 int err = 0;
149 150
150 if (class == PASCAL_B && g->gr.ctx_vars.force_preemption_gfxp) 151 if (class == PASCAL_B && g->gr.ctx_vars.force_preemption_gfxp) {
151 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; 152 graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP;
153 }
152 154
153 if (class == PASCAL_COMPUTE_B && 155 if (class == PASCAL_COMPUTE_B &&
154 g->gr.ctx_vars.force_preemption_cilp) 156 g->gr.ctx_vars.force_preemption_cilp) {
155 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; 157 compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP;
158 }
156 159
157 /* check for invalid combinations */ 160 /* check for invalid combinations */
158 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) 161 if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) {
159 return -EINVAL; 162 return -EINVAL;
163 }
160 164
161 if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && 165 if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) &&
162 (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) 166 (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) {
163 return -EINVAL; 167 return -EINVAL;
168 }
164 169
165 /* set preemption modes */ 170 /* set preemption modes */
166 switch (graphics_preempt_mode) { 171 switch (graphics_preempt_mode) {