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authorseshendra Gadagottu <sgadagottu@nvidia.com>2018-01-02 18:48:46 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-01-10 11:47:03 -0500
commit0ac3ba2a99b745f577c752ebf9a6b4291730a36d (patch)
treedd111702d91dd5d14369def5fc152960f90a2daf /drivers/gpu/nvgpu/gp106/gr_gp106.c
parent3e9aa581b61a3ecbcf01a8988b1d12a8af8e2a45 (diff)
gpu: nvgpu: gv11b: fix for gfx preemption
Used chip specific attrib_cb_gfxp_default_size and attrib_cb_gfxp_size buffer sizes during committing global callback buffer when gfx preemption is requested. These sizes are different for gv11b from gp10b. For gp10b used smaller buffer sizes than specified value in hw manuals as per sw requirement. Also used gv11b specific preemption related functions: gr_gv11b_set_ctxsw_preemption_mode gr_gv11b_update_ctxsw_preemption_mode This is required because preemption related buffer sizes are different for gv11b from gp10b. More optimization will be done as part of NVGPU-484. Another issue fixed is: gpu va for preemption buffers still needs to be 8 bit aligned, even though 49 bits available now. This done because of legacy implementation of fecs ucode. Bug 1976694 Change-Id: I2dc923340d34d0dc5fe45419200d0cf4f53cdb23 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1635027 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao <rizhao@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/gr_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/gr_gp106.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c
index af08aa6c..bedc0b78 100644
--- a/drivers/gpu/nvgpu/gp106/gr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP106 GPU GR 2 * GP106 GPU GR
3 * 3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -128,6 +128,10 @@ void gr_gp106_cb_size_default(struct gk20a *g)
128 gr->attrib_cb_default_size = 0x800; 128 gr->attrib_cb_default_size = 0x800;
129 gr->alpha_cb_default_size = 129 gr->alpha_cb_default_size =
130 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 130 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
131 gr->attrib_cb_gfxp_default_size =
132 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
133 gr->attrib_cb_gfxp_size =
134 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v();
131} 135}
132 136
133int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g, 137int gr_gp106_set_ctxsw_preemption_mode(struct gk20a *g,