gpu: nvgpu: Add gp106 clock gating tables

JIRA DNVGPU-72
JIRA DNVGPU-73

Change-Id: I4a979344649ced1bbf8df215c07a15b6149bba69
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1215915
(cherry picked from commit d5f49042010a18e2885e1213b463cb067d765390)
Reviewed-on: http://git-master/r/1227267
GVS: Gerrit_Virtual_Submit

1 files changed, 649 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c
new file mode 100644
index 00000000..29870d60
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c
@@ -0,0 +1,649 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * This file is autogenerated.  Do not edit.
+ */
+
+#ifndef __gp106_gating_reglist_h__
+#define __gp106_gating_reglist_h__
+
+#include <linux/types.h>
+#include "gp106_gating_reglist.h"
+
+struct gating_desc {
+        u32 addr;
+        u32 prod;
+        u32 disable;
+};
+/* slcg bus */
+static const struct gating_desc gp106_slcg_bus[] = {
+        {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe},
+};
+
+/* slcg ce2 */
+static const struct gating_desc gp106_slcg_ce2[] = {
+        {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe},
+};
+
+/* slcg chiplet */
+static const struct gating_desc gp106_slcg_chiplet[] = {
+        {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c0fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c17c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c1fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c27c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010c2fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d0fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d17c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d1fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d27c, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010d2fc, .prod = 0x00000000, .disable = 0x00000007},
+        {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007},
+};
+
+/* slcg fb */
+static const struct gating_desc gp106_slcg_fb[] = {
+        {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe},
+};
+
+/* slcg fifo */
+static const struct gating_desc gp106_slcg_fifo[] = {
+        {.addr = 0x000026ac, .prod = 0x00000000, .disable = 0x0001fffe},
+};
+
+/* slcg gr */
+static const struct gating_desc gp106_slcg_gr[] = {
+        {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x07fffffe},
+        {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe},
+        {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe},
+        {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe},
+        {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe},
+        {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe},
+        {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe},
+        {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe},
+        {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e},
+        {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x000003fe},
+        {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001},
+        {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00418c74, .prod = 0xffffff80, .disable = 0xfffffffe},
+        {.addr = 0x00418cf4, .prod = 0xfffffff8, .disable = 0xfffffffe},
+        {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe},
+        {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe},
+        {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe},
+        {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe},
+        {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff},
+        {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e},
+        {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe},
+        {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e},
+        {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e},
+        {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe},
+        {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe},
+        {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe},
+        {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e},
+        {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe},
+        {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe},
+        {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe},
+        {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe},
+        {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe},
+        {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe},
+        {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe},
+        {.addr = 0x00412814, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412a84, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x004129ac, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412a24, .prod = 0x00000000, .disable = 0x0000ffff},
+        {.addr = 0x00412c14, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412e84, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412dac, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00412e24, .prod = 0x00000000, .disable = 0x0000ffff},
+        {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe},
+        {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff},
+};
+
+/* slcg ltc */
+static const struct gating_desc gp106_slcg_ltc[] = {
+        {.addr = 0x00154050, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015455c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015475c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015435c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x00156050, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015655c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015675c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0015635c, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe},
+};
+
+/* slcg perf */
+static const struct gating_desc gp106_slcg_perf[] = {
+        {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc218, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc418, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc618, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bc818, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001bca18, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8218, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8418, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8618, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8818, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b8a18, .prod = 0x000001ff, .disable = 0x00000000},
+        {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000},
+};
+
+/* slcg PriRing */
+static const struct gating_desc gp106_slcg_priring[] = {
+        {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001},
+};
+
+/* slcg pmu */
+static const struct gating_desc gp106_slcg_pmu[] = {
+        {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe},
+        {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe},
+        {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* therm gr */
+static const struct gating_desc gp106_slcg_therm[] = {
+        {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f},
+};
+
+/* slcg Xbar */
+static const struct gating_desc gp106_slcg_xbar[] = {
+        {.addr = 0x0013c824, .prod = 0x00000000, .disable = 0x7ffffffe},
+        {.addr = 0x0013dc08, .prod = 0x00000000, .disable = 0xfffffffe},
+        {.addr = 0x0013c924, .prod = 0x00000000, .disable = 0x7ffffffe},
+        {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc24, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc44, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc64, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cc84, .prod = 0x00000000, .disable = 0x1ffffffe},
+        {.addr = 0x0013cca4, .prod = 0x00000000, .disable = 0x1ffffffe},
+};
+
+/* blcg bus */
+static const struct gating_desc gp106_blcg_bus[] = {
+        {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* blcg ce */
+static const struct gating_desc gp106_blcg_ce[] = {
+        {.addr = 0x00104200, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg fb */
+static const struct gating_desc gp106_blcg_fb[] = {
+        {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000},
+        {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000},
+};
+
+/* blcg fifo */
+static const struct gating_desc gp106_blcg_fifo[] = {
+        {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg gr */
+static const struct gating_desc gp106_blcg_gr[] = {
+        {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000},
+        {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000},
+        {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000},
+        {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000},
+        {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000},
+        {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000},
+        {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000},
+        {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000},
+        {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000},
+        {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000},
+        {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000},
+        {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000},
+        {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000},
+        {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000},
+        {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000},
+        {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000},
+        {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000},
+        {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000},
+        {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000},
+        {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000},
+        {.addr = 0x00412810, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412a80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x004129a8, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412c10, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412e80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00412da8, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000},
+        {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000},
+};
+
+/* blcg ltc */
+static const struct gating_desc gp106_blcg_ltc[] = {
+        {.addr = 0x00154030, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x00154040, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001545e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001545c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001547e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001547c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001543e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001543c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x00156030, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x00156040, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001565e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001565c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001567e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001567c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001563e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x001563c8, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000},
+        {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000},
+};
+
+/* blcg pmu */
+static const struct gating_desc gp106_blcg_pmu[] = {
+        {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000},
+};
+
+/* blcg Xbar */
+static const struct gating_desc gp106_blcg_xbar[] = {
+        {.addr = 0x0013c820, .prod = 0x0001004a, .disable = 0x00000000},
+        {.addr = 0x0013dc04, .prod = 0x0001004a, .disable = 0x00000000},
+        {.addr = 0x0013c920, .prod = 0x0000004a, .disable = 0x00000000},
+        {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc20, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc40, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc60, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cc80, .prod = 0x00000042, .disable = 0x00000000},
+        {.addr = 0x0013cca0, .prod = 0x00000042, .disable = 0x00000000},
+};
+
+/* pg gr */
+static const struct gating_desc gp106_pg_gr[] = {
+};
+
+/* inline functions */
+void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_bus[i].addr,
+                                gp106_slcg_bus[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_bus[i].addr,
+                                 gp106_slcg_bus[i].disable);
+        }
+}
+
+void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_ce2[i].addr,
+                                gp106_slcg_ce2[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_ce2[i].addr,
+                                 gp106_slcg_ce2[i].disable);
+        }
+}
+
+void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_chiplet[i].addr,
+                                gp106_slcg_chiplet[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_chiplet[i].addr,
+                                 gp106_slcg_chiplet[i].disable);
+        }
+}
+
+void gp106_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+}
+
+void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_fb[i].addr,
+                                gp106_slcg_fb[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_fb[i].addr,
+                                 gp106_slcg_fb[i].disable);
+        }
+}
+
+void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_fifo[i].addr,
+                                gp106_slcg_fifo[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_fifo[i].addr,
+                                 gp106_slcg_fifo[i].disable);
+        }
+}
+
+void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_gr[i].addr,
+                                gp106_slcg_gr[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_gr[i].addr,
+                                 gp106_slcg_gr[i].disable);
+        }
+}
+
+void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_ltc[i].addr,
+                                gp106_slcg_ltc[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_ltc[i].addr,
+                                gp106_slcg_ltc[i].disable);
+        }
+}
+
+void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_perf[i].addr,
+                                gp106_slcg_perf[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_perf[i].addr,
+                                gp106_slcg_perf[i].disable);
+        }
+}
+
+void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_priring[i].addr,
+                                gp106_slcg_priring[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_priring[i].addr,
+                                gp106_slcg_priring[i].disable);
+        }
+}
+
+void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_pmu[i].addr,
+                                gp106_slcg_pmu[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_pmu[i].addr,
+                                gp106_slcg_pmu[i].disable);
+        }
+}
+
+void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_therm[i].addr,
+                                gp106_slcg_therm[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_therm[i].addr,
+                                gp106_slcg_therm[i].disable);
+        }
+}
+
+void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_slcg_xbar[i].addr,
+                                gp106_slcg_xbar[i].prod);
+                else
+                        gk20a_writel(g, gp106_slcg_xbar[i].addr,
+                                gp106_slcg_xbar[i].disable);
+        }
+}
+
+void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_bus[i].addr,
+                                gp106_blcg_bus[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_bus[i].addr,
+                                gp106_blcg_bus[i].disable);
+        }
+}
+
+void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_ce[i].addr,
+                                gp106_blcg_ce[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_ce[i].addr,
+                                gp106_blcg_ce[i].disable);
+        }
+}
+
+void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_fb[i].addr,
+                                gp106_blcg_fb[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_fb[i].addr,
+                                gp106_blcg_fb[i].disable);
+        }
+}
+
+void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_fifo[i].addr,
+                                gp106_blcg_fifo[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_fifo[i].addr,
+                                gp106_blcg_fifo[i].disable);
+        }
+}
+
+void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_gr[i].addr,
+                                gp106_blcg_gr[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_gr[i].addr,
+                                gp106_blcg_gr[i].disable);
+        }
+}
+
+void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_ltc[i].addr,
+                                gp106_blcg_ltc[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_ltc[i].addr,
+                                gp106_blcg_ltc[i].disable);
+        }
+}
+
+void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_pmu[i].addr,
+                                gp106_blcg_pmu[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_pmu[i].addr,
+                                gp106_blcg_pmu[i].disable);
+        }
+}
+
+void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_blcg_xbar[i].addr,
+                                gp106_blcg_xbar[i].prod);
+                else
+                        gk20a_writel(g, gp106_blcg_xbar[i].addr,
+                                gp106_blcg_xbar[i].disable);
+        }
+}
+
+void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
+        bool prod)
+{
+        u32 i;
+        u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc);
+        for (i = 0; i < size; i++) {
+                if (prod)
+                        gk20a_writel(g, gp106_pg_gr[i].addr,
+                                gp106_pg_gr[i].prod);
+                else
+                        gk20a_writel(g, gp106_pg_gr[i].addr,
+                                gp106_pg_gr[i].disable);
+        }
+}
+
+#endif /* __gp106_gating_reglist_h__ */