gpu: nvgpu: skip clk gating prog for sim/emu.

For Simualtion/Emulation platforms,clock gating
should be skipped as it is not supported.
Added new flags "can_"X"lcg" to check platform
capability before doing SLCG,BLCG and ELCG.

Bug 200314250

Change-Id: I4124d444a77a4c06df8c1d82c6038bfd457f3db0
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566049
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 85 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c
index 5a634313..169a1fee 100644
--- a/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c
+++ b/drivers/gpu/nvgpu/gp106/gp106_gating_reglist.c
@@ -26,6 +26,7 @@
 #define __gp106_gating_reglist_h__
 
 #include "gp106_gating_reglist.h"
+#include <nvgpu/enabled.h>
 
 struct gating_desc {
         u32 addr;
@@ -276,6 +277,10 @@ void gp106_slcg_bus_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_bus) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_bus[i].addr,
@@ -291,6 +296,10 @@ void gp106_slcg_ce2_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_ce2) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_ce2[i].addr,
@@ -306,6 +315,10 @@ void gp106_slcg_chiplet_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_chiplet) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_chiplet[i].addr,
@@ -326,6 +339,10 @@ void gp106_slcg_fb_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_fb) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_fb[i].addr,
@@ -341,6 +358,10 @@ void gp106_slcg_fifo_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_fifo) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_fifo[i].addr,
@@ -356,6 +377,10 @@ void gr_gp106_slcg_gr_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_gr) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_gr[i].addr,
@@ -371,6 +396,10 @@ void ltc_gp106_slcg_ltc_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_ltc) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_ltc[i].addr,
@@ -386,6 +415,10 @@ void gp106_slcg_perf_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_perf) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_perf[i].addr,
@@ -401,6 +434,10 @@ void gp106_slcg_priring_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_priring) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_priring[i].addr,
@@ -416,6 +453,10 @@ void gp106_slcg_pmu_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_pmu) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_pmu[i].addr,
@@ -431,6 +472,10 @@ void gp106_slcg_therm_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_therm) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_therm[i].addr,
@@ -446,6 +491,10 @@ void gp106_slcg_xbar_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_slcg_xbar) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_slcg_xbar[i].addr,
@@ -461,6 +510,10 @@ void gp106_blcg_bus_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_bus) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_bus[i].addr,
@@ -476,6 +529,10 @@ void gp106_blcg_ce_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_ce) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_ce[i].addr,
@@ -491,6 +548,10 @@ void gp106_blcg_fb_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_fb) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_fb[i].addr,
@@ -506,6 +567,10 @@ void gp106_blcg_fifo_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_fifo) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_fifo[i].addr,
@@ -521,6 +586,10 @@ void gp106_blcg_gr_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_gr) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_gr[i].addr,
@@ -536,6 +605,10 @@ void gp106_blcg_ltc_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_ltc) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_ltc[i].addr,
@@ -551,6 +624,10 @@ void gp106_blcg_pmu_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_pmu) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_pmu[i].addr,
@@ -566,6 +643,10 @@ void gp106_blcg_xbar_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_blcg_xbar) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_blcg_xbar[i].addr,
@@ -581,6 +662,10 @@ void gr_gp106_pg_gr_load_gating_prod(struct gk20a *g,
 {
         u32 i;
         u32 size = sizeof(gp106_pg_gr) / sizeof(struct gating_desc);
+
+        if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG))
+                return;
+
         for (i = 0; i < size; i++) {
                 if (prod)
                         gk20a_writel(g, gp106_pg_gr[i].addr,