diff options
author | David Nieto <dmartineznie@nvidia.com> | 2016-08-08 06:13:37 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:49 -0500 |
commit | d2b67f1ad606733a63d8261e36068e5bd1f96cdc (patch) | |
tree | ff04e59f649ac9fddafc16832f088670440660bc /drivers/gpu/nvgpu/gp106/clk_gp106.c | |
parent | 432017248e432df0619dc2df30f915a52634338f (diff) |
gpu: nvgpu: add debugfs to dump clocks
* Removed unused registers from headers
* Added counter based MCLK
* Removed hardcoding
JIRA DNVGPU-98
Change-Id: Idffcd7fc17024582b41c29371a2295df8f0c206b
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1204019
(cherry picked from commit 48dfa41a641c3adbc4d25a35f418cf73b08d5e8c)
Reviewed-on: http://git-master/r/1227264
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/clk_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 226 |
1 files changed, 226 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c new file mode 100644 index 00000000..4bf03661 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -0,0 +1,226 @@ | |||
1 | /* | ||
2 | * GP106 Clocks | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/clk.h> | ||
20 | #include <linux/delay.h> /* for mdelay */ | ||
21 | #include <linux/module.h> | ||
22 | #include <linux/debugfs.h> | ||
23 | #include <linux/uaccess.h> | ||
24 | #include <linux/clk/tegra.h> | ||
25 | #include <linux/tegra-fuse.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | #include "hw_trim_gp106.h" | ||
29 | #include "clk_gp106.h" | ||
30 | |||
31 | #define gk20a_dbg_clk(fmt, arg...) \ | ||
32 | gk20a_dbg(gpu_dbg_clk, fmt, ##arg) | ||
33 | |||
34 | #ifdef CONFIG_DEBUG_FS | ||
35 | static int clk_gp106_debugfs_init(struct gk20a *g); | ||
36 | #endif | ||
37 | |||
38 | #define NUM_NAMEMAPS 4 | ||
39 | |||
40 | static int gp106_init_clk_support(struct gk20a *g) { | ||
41 | struct clk_gk20a *clk = &g->clk; | ||
42 | u32 err = 0; | ||
43 | |||
44 | gk20a_dbg_fn(""); | ||
45 | |||
46 | mutex_init(&clk->clk_mutex); | ||
47 | |||
48 | clk->clk_namemap = (struct namemap_cfg *) | ||
49 | kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL); | ||
50 | |||
51 | if (!clk->clk_namemap) | ||
52 | return -ENOMEM; | ||
53 | |||
54 | clk->clk_namemap[0] = (struct namemap_cfg) { | ||
55 | .namemap = CLK_NAMEMAP_INDEX_GPC2CLK, | ||
56 | .is_enable = 1, | ||
57 | .is_counter = 1, | ||
58 | .g = g, | ||
59 | .cntr.reg_ctrl_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(), | ||
60 | .cntr.reg_ctrl_idx = | ||
61 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(), | ||
62 | .cntr.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(), | ||
63 | .name = "gpc2clk" | ||
64 | }; | ||
65 | clk->clk_namemap[1] = (struct namemap_cfg) { | ||
66 | .namemap = CLK_NAMEMAP_INDEX_SYS2CLK, | ||
67 | .is_enable = 1, | ||
68 | .is_counter = 1, | ||
69 | .g = g, | ||
70 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(), | ||
71 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(), | ||
72 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r(), | ||
73 | .name = "sys2clk" | ||
74 | }; | ||
75 | clk->clk_namemap[2] = (struct namemap_cfg) { | ||
76 | .namemap = CLK_NAMEMAP_INDEX_XBAR2CLK, | ||
77 | .is_enable = 1, | ||
78 | .is_counter = 1, | ||
79 | .g = g, | ||
80 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(), | ||
81 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(), | ||
82 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r(), | ||
83 | .name = "xbar2clk" | ||
84 | }; | ||
85 | clk->clk_namemap[3] = (struct namemap_cfg) { | ||
86 | .namemap = CLK_NAMEMAP_INDEX_DRAMCLK, | ||
87 | .is_enable = 1, | ||
88 | .is_counter = 1, | ||
89 | .g = g, | ||
90 | .cntr.reg_ctrl_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(), | ||
91 | .cntr.reg_ctrl_idx = | ||
92 | trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(), | ||
93 | .cntr.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(), | ||
94 | .name = "dramdiv2_rec_clk1" | ||
95 | }; | ||
96 | |||
97 | clk->namemap_num = NUM_NAMEMAPS; | ||
98 | |||
99 | clk->g = g; | ||
100 | |||
101 | #ifdef CONFIG_DEBUG_FS | ||
102 | if (!clk->debugfs_set) { | ||
103 | if (!clk_gp106_debugfs_init(g)) | ||
104 | clk->debugfs_set = true; | ||
105 | } | ||
106 | #endif | ||
107 | return err; | ||
108 | } | ||
109 | |||
110 | #ifdef CONFIG_DEBUG_FS | ||
111 | typedef struct namemap_cfg namemap_cfg_t; | ||
112 | static u32 gp106_get_rate_cntr(struct gk20a *, struct namemap_cfg *); | ||
113 | |||
114 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { | ||
115 | u32 save_reg; | ||
116 | u32 retries; | ||
117 | u32 cntr = 0; | ||
118 | |||
119 | struct clk_gk20a *clk = &g->clk; | ||
120 | |||
121 | if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr) | ||
122 | return 0; | ||
123 | |||
124 | mutex_lock(&clk->clk_mutex); | ||
125 | |||
126 | /* Save the register */ | ||
127 | save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
128 | |||
129 | /* Disable and reset the current clock */ | ||
130 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
131 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | | ||
132 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | ||
133 | |||
134 | /* Force wb() */ | ||
135 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
136 | |||
137 | /* Wait for reset to happen */ | ||
138 | retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES; | ||
139 | do { | ||
140 | udelay(CLK_DEFAULT_CNTRL_SETTLE_USECS); | ||
141 | } while ((--retries) && (cntr = gk20a_readl(g, c->cntr.reg_cntr_addr))); | ||
142 | |||
143 | if (!retries) { | ||
144 | gk20a_err(dev_from_gk20a(g), | ||
145 | "unable to settle counter reset, bailing"); | ||
146 | goto read_err; | ||
147 | } | ||
148 | /* Program counter */ | ||
149 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
150 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() | | ||
151 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f() | | ||
152 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
153 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
154 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
155 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) | | ||
156 | c->cntr.reg_ctrl_idx); | ||
157 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
158 | |||
159 | udelay(XTAL_CNTR_DELAY); | ||
160 | |||
161 | cntr = XTAL_SCALE_TO_KHZ * gk20a_readl(g, c->cntr.reg_cntr_addr); | ||
162 | |||
163 | read_err: | ||
164 | /* reset and restore control register */ | ||
165 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
166 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | | ||
167 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | ||
168 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
169 | gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); | ||
170 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
171 | mutex_unlock(&clk->clk_mutex); | ||
172 | |||
173 | return cntr; | ||
174 | |||
175 | } | ||
176 | |||
177 | static int gp106_get_rate_show(void *data , u64 *val) { | ||
178 | struct namemap_cfg *c = (struct namemap_cfg *) data; | ||
179 | struct gk20a *g = c->g; | ||
180 | |||
181 | *val = c->is_counter ? gp106_get_rate_cntr(g, c) : 0 /* TODO PLL read */; | ||
182 | return 0; | ||
183 | } | ||
184 | DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n"); | ||
185 | |||
186 | |||
187 | static int clk_gp106_debugfs_init(struct gk20a *g) { | ||
188 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
189 | |||
190 | struct dentry *gpu_root = platform->debugfs; | ||
191 | struct dentry *clocks_root; | ||
192 | struct dentry *d; | ||
193 | int i; | ||
194 | |||
195 | if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root))) | ||
196 | return -ENOMEM; | ||
197 | |||
198 | gk20a_dbg(gpu_dbg_info, "g=%p", g); | ||
199 | |||
200 | for (i = 0; i < g->clk.namemap_num; i++) { | ||
201 | if (g->clk.clk_namemap[i].is_enable) { | ||
202 | d = debugfs_create_file( | ||
203 | g->clk.clk_namemap[i].name, | ||
204 | S_IRUGO, | ||
205 | clocks_root, | ||
206 | &g->clk.clk_namemap[i], | ||
207 | &get_rate_fops); | ||
208 | if (!d) | ||
209 | goto err_out; | ||
210 | } | ||
211 | } | ||
212 | return 0; | ||
213 | |||
214 | err_out: | ||
215 | pr_err("%s: Failed to make debugfs node\n", __func__); | ||
216 | debugfs_remove_recursive(clocks_root); | ||
217 | return -ENOMEM; | ||
218 | } | ||
219 | |||
220 | #endif /* CONFIG_DEBUG_FS */ | ||
221 | |||
222 | void gp106_init_clk_ops(struct gpu_ops *gops) { | ||
223 | gops->clk.init_clk_support = gp106_init_clk_support; | ||
224 | } | ||
225 | |||
226 | |||