nvgpu: gpu: Add debugfs nodes for CFC control

Develop a file heirarchy to hold clock frequency
controller(CFC) related debugfs nodes.
/gpu_root -> /clk_freq_ctlr
		-> sys
		-> ltc
		-> xbar
		-> gpc
Reading the file should tell if the particular
CFC is enabled(1) or disabled(0). Write 0 to
the file to disable the CFC and 1 to enable the
CFC. We can write 0 to all the files to disable
all CFCs.

JIRA DNVGPU-207

DEPENDS ON: <http://git-master/r/1563303>

Change-Id: I845a4aab8b1195b24fe2377a697c1de0cfe9ecfd
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563302
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 122 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index a7448cad..4b941433 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -242,18 +242,139 @@ static int gp106_get_rate_show(void *data , u64 *val) {
 }
 DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n");
 
+static int sys_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int sys_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n");
+
+static int ltc_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int ltc_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n");
+
+static int xbar_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int xbar_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read,
+                        xbar_cfc_write, "%llu\n");
+
+static int gpc_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int gpc_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n");
 
 static int clk_gp106_debugfs_init(struct gk20a *g)
 {
         struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
         struct dentry *gpu_root = l->debugfs;
-        struct dentry *clocks_root;
+        struct dentry *clocks_root, *clk_freq_ctlr_root;
         struct dentry *d;
         unsigned int i;
 
         if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
                 return -ENOMEM;
 
+        clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root);
+        if (clk_freq_ctlr_root == NULL)
+                return -ENOMEM;
+
+        d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &sys_cfc_fops);
+        d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &ltc_cfc_fops);
+        d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &xbar_cfc_fops);
+        d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &gpc_cfc_fops);
+
         gk20a_dbg(gpu_dbg_info, "g=%p", g);
 
         for (i = 0; i < g->clk.namemap_num; i++) {