diff options
author | Sunny He <suhe@nvidia.com> | 2017-06-29 17:24:29 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-02 17:43:27 -0400 |
commit | 11e29991acd25baef5b786605e136b5e71737b8e (patch) | |
tree | 1fd738a07e172ef7cdc2882359424be246964ce3 /drivers/gpu/nvgpu/gp106/clk_gp106.c | |
parent | a15e110a9b790f55a5c6e257cfbf7f7235f5a334 (diff) |
gpu: nvgpu: Reorg clk HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the clk
and clk_arb sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I553353df836b187b8eac61e16b63080b570c96b8
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1511076
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/clk_gp106.c')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index e9aec7ac..105f8bd5 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -47,12 +47,12 @@ static int clk_gp106_debugfs_init(struct gk20a *g); | |||
47 | 47 | ||
48 | 48 | ||
49 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *); | 49 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *); |
50 | static u32 gp106_crystal_clk_hz(struct gk20a *g) | 50 | u32 gp106_crystal_clk_hz(struct gk20a *g) |
51 | { | 51 | { |
52 | return (XTAL4X_KHZ * 1000); | 52 | return (XTAL4X_KHZ * 1000); |
53 | } | 53 | } |
54 | 54 | ||
55 | static unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain) | 55 | unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain) |
56 | { | 56 | { |
57 | struct clk_gk20a *clk = &g->clk; | 57 | struct clk_gk20a *clk = &g->clk; |
58 | u32 freq_khz; | 58 | u32 freq_khz; |
@@ -76,7 +76,8 @@ static unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain) | |||
76 | return freq_khz * 1000UL; | 76 | return freq_khz * 1000UL; |
77 | } | 77 | } |
78 | 78 | ||
79 | static int gp106_init_clk_support(struct gk20a *g) { | 79 | int gp106_init_clk_support(struct gk20a *g) |
80 | { | ||
80 | struct clk_gk20a *clk = &g->clk; | 81 | struct clk_gk20a *clk = &g->clk; |
81 | u32 err = 0; | 82 | u32 err = 0; |
82 | 83 | ||
@@ -273,18 +274,8 @@ err_out: | |||
273 | } | 274 | } |
274 | #endif /* CONFIG_DEBUG_FS */ | 275 | #endif /* CONFIG_DEBUG_FS */ |
275 | 276 | ||
276 | static int gp106_suspend_clk_support(struct gk20a *g) | 277 | int gp106_suspend_clk_support(struct gk20a *g) |
277 | { | 278 | { |
278 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | 279 | nvgpu_mutex_destroy(&g->clk.clk_mutex); |
279 | return 0; | 280 | return 0; |
280 | } | 281 | } |
281 | |||
282 | void gp106_init_clk_ops(struct gpu_ops *gops) { | ||
283 | gops->clk.init_clk_support = gp106_init_clk_support; | ||
284 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; | ||
285 | gops->clk.measure_freq = gp106_clk_measure_freq; | ||
286 | gops->clk.suspend_clk_support = gp106_suspend_clk_support; | ||
287 | gops->clk.mclk_init = gp106_mclk_init; | ||
288 | gops->clk.mclk_change = gp106_mclk_change; | ||
289 | gops->clk.mclk_deinit = gp106_mclk_deinit; | ||
290 | } | ||