gpu: nvgpu: gp106: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces, introducing the braces.

JIRA NVGPU-671

Change-Id: I8493274995ed8de526902dd0ca0808b2972e28aa
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796806
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 10 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
index 5f969e79..ca8015d6 100644
--- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
@@ -55,20 +55,24 @@ int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
 
         p5_info = pstate_get_clk_set_info(g,
                         CTRL_PERF_PSTATE_P5, clkwhich);
-        if (!p5_info)
+        if (!p5_info) {
                 return -EINVAL;
+        }
 
         p0_info = pstate_get_clk_set_info(g,
                         CTRL_PERF_PSTATE_P0, clkwhich);
-        if (!p0_info)
+        if (!p0_info) {
                 return -EINVAL;
+        }
 
         limit_min_mhz = p5_info->min_mhz;
         /* WAR for DVCO min */
-        if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK)
+        if (api_domain == CTRL_CLK_DOMAIN_GPC2CLK) {
                 if ((pfllobjs->max_min_freq_mhz) &&
-                (pfllobjs->max_min_freq_mhz >= limit_min_mhz))
+                        (pfllobjs->max_min_freq_mhz >= limit_min_mhz)) {
                         limit_min_mhz = pfllobjs->max_min_freq_mhz + 1;
+                }
+        }
 
         *min_mhz = limit_min_mhz;
         *max_mhz = p0_info->max_mhz;
@@ -97,8 +101,9 @@ int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
 
         p0_info = pstate_get_clk_set_info(g,
                         CTRL_PERF_PSTATE_P0, clkwhich);
-        if (!p0_info)
+        if (!p0_info) {
                 return -EINVAL;
+        }
 
         *default_mhz = p0_info->max_mhz;