nvgpu: gpu: arbiter for vf switch management

JIRA DNVGPU-143

The arbiter is charged with selecting the proper
frequencies when multiple applications submit
simultaneously clock change requests

On the current implementation, the arbiter guarantees
that the selected frequency will be always higher
or equal to the request, as long as the request is
in range.

The current code is not yet realtime friendly, as
requests are not pre-allocated.

Summary of changes:
(1) pstate/vf switch no longer selects boot frequency
(2) changed mclk code change to accept input freq
(3) added arbiter
(4) now a single session can submit concurrent requests
the last request is the one that applies for that
session
(5) modified locking mechanism to reduce lock contention
(6) Added callback to notify the arbiter that the VF
table has changed and is no longer valid (PMU/Thermals
must call this when VF table is invalid)
(7) changed internal API to work with MHz
(8) added debugfs for stats

Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239461
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267120
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 5 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
index 112cb588..d1cbb32b 100644
--- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
@@ -23,7 +23,7 @@ static u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
 }
 
 static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
-                u64 *min_hz, u64 *max_hz)
+                u16 *min_mhz, u16 *max_mhz)
 {
         enum nv_pmu_clk_clkwhich clkwhich;
         struct clk_set_info *p0_info;
@@ -52,14 +52,14 @@ static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
         if (!p0_info)
                 return -EINVAL;
 
-        *min_hz = (u64)(p5_info->min_mhz) * (u64)MHZ;
-        *max_hz = (u64)(p0_info->max_mhz) * (u64)MHZ;
+        *min_mhz = p5_info->min_mhz;
+        *max_mhz = p0_info->max_mhz;
 
         return 0;
 }
 
 static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
-                u64 *default_hz)
+                u16 *default_mhz)
 {
         enum nv_pmu_clk_clkwhich clkwhich;
         struct clk_set_info *p0_info;
@@ -82,7 +82,7 @@ static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
         if (!p0_info)
                 return -EINVAL;
 
-        *default_hz = (u64)p0_info->max_mhz * (u64)MHZ;
+        *default_mhz = p0_info->max_mhz;
 
         return 0;
 }