gpu: nvgpu: clk requests completion and event fds

Install one completion fd per SET request.
Notifications on dedicated event fd.
Changed frequencies unit to Hz from MHz.
Remove sequence numbers from dummy arbiter.
Added effective clock type (query frequency from counters).

Jira DNVGPU-125

Change-Id: Id5445c6ae1d6bf06f7f59c82ff6c5d3b34e26483
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1230239
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit d17083f4ceb69725c661678607a3e43148d38560)
Reviewed-on: http://git-master/r/1243106

1 files changed, 5 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
index d1cbb32b..112cb588 100644
--- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
@@ -23,7 +23,7 @@ static u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
 }
 
 static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
-                u16 *min_mhz, u16 *max_mhz)
+                u64 *min_hz, u64 *max_hz)
 {
         enum nv_pmu_clk_clkwhich clkwhich;
         struct clk_set_info *p0_info;
@@ -52,14 +52,14 @@ static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
         if (!p0_info)
                 return -EINVAL;
 
-        *min_mhz = p5_info->min_mhz;
-        *max_mhz = p0_info->max_mhz;
+        *min_hz = (u64)(p5_info->min_mhz) * (u64)MHZ;
+        *max_hz = (u64)(p0_info->max_mhz) * (u64)MHZ;
 
         return 0;
 }
 
 static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
-                u16 *default_mhz)
+                u64 *default_hz)
 {
         enum nv_pmu_clk_clkwhich clkwhich;
         struct clk_set_info *p0_info;
@@ -82,7 +82,7 @@ static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
         if (!p0_info)
                 return -EINVAL;
 
-        *default_mhz = p0_info->max_mhz;
+        *default_hz = (u64)p0_info->max_mhz * (u64)MHZ;
 
         return 0;
 }