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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-09-20 11:48:34 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:49 -0500
commitcb80abb2d2bee2f9feb987b83e8b106acdf14373 (patch)
tree62c8283ec2bd702066bb921b298b3e7a6663f40b /drivers/gpu/nvgpu/gp106/acr_gp106.c
parent41838fc2bb6135bdd87d080a1efda8403f6f2657 (diff)
gpu: nvgpu: Suppress error msg from VBIOS overlay
Suppress error message when nvgpu tries to load VBIOS overlay, but one is not found. This situation is normal. This is done by moving gk20a_request_firmware() to be nvgpu generic function nvgpu_request_firmware(), and adding a NO_WARN flag to it. Introduce also a NO_SOC flag to suppress attempt to load firmware from SoC specific directory in addition to the chip specific directory. Use it for dGPU firmware files. Bug 200236777 Change-Id: I4666bee512ae0914ef92b75f068685cb2b503cc8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1223839 (cherry picked from commit e9ae74dfbde3c3d2b103e1927aa92ec7d97cd76d) Reviewed-on: http://git-master/r/1233412 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gp106/acr_gp106.c')
-rw-r--r--drivers/gpu/nvgpu/gp106/acr_gp106.c30
1 files changed, 22 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c
index e47c4eb1..39371666 100644
--- a/drivers/gpu/nvgpu/gp106/acr_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c
@@ -28,6 +28,7 @@
28#include "gm206/pmu_gm206.h" 28#include "gm206/pmu_gm206.h"
29#include "sec2_gp106.h" 29#include "sec2_gp106.h"
30#include "nvgpu_gpuid_t18x.h" 30#include "nvgpu_gpuid_t18x.h"
31#include "nvgpu_common.h"
31 32
32/*Defines*/ 33/*Defines*/
33#define gp106_dbg_pmu(fmt, arg...) \ 34#define gp106_dbg_pmu(fmt, arg...) \
@@ -138,7 +139,8 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
138 int err; 139 int err;
139 140
140 gp106_dbg_pmu("requesting PMU ucode in gp106\n"); 141 gp106_dbg_pmu("requesting PMU ucode in gp106\n");
141 pmu_fw = gk20a_request_firmware(g, GM20B_PMU_UCODE_IMAGE); 142 pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE,
143 NVGPU_REQUEST_FIRMWARE_NO_SOC);
142 if (!pmu_fw) { 144 if (!pmu_fw) {
143 gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode!!"); 145 gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode!!");
144 return -ENOENT; 146 return -ENOENT;
@@ -147,13 +149,15 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
147 gp106_dbg_pmu("Loaded PMU ucode in for blob preparation"); 149 gp106_dbg_pmu("Loaded PMU ucode in for blob preparation");
148 150
149 gp106_dbg_pmu("requesting PMU ucode desc in GM20B\n"); 151 gp106_dbg_pmu("requesting PMU ucode desc in GM20B\n");
150 pmu_desc = gk20a_request_firmware(g, GM20B_PMU_UCODE_DESC); 152 pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC,
153 NVGPU_REQUEST_FIRMWARE_NO_SOC);
151 if (!pmu_desc) { 154 if (!pmu_desc) {
152 gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!"); 155 gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!");
153 err = -ENOENT; 156 err = -ENOENT;
154 goto release_img_fw; 157 goto release_img_fw;
155 } 158 }
156 pmu_sig = gk20a_request_firmware(g, GM20B_PMU_UCODE_SIG); 159 pmu_sig = nvgpu_request_firmware(g, GM20B_PMU_UCODE_SIG,
160 NVGPU_REQUEST_FIRMWARE_NO_SOC);
157 if (!pmu_sig) { 161 if (!pmu_sig) {
158 gk20a_err(dev_from_gk20a(g), "failed to load pmu sig!!"); 162 gk20a_err(dev_from_gk20a(g), "failed to load pmu sig!!");
159 err = -ENOENT; 163 err = -ENOENT;
@@ -206,10 +210,14 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
206 210
207 switch (ver) { 211 switch (ver) {
208 case NVGPU_GPUID_GP104: 212 case NVGPU_GPUID_GP104:
209 fecs_sig = gk20a_request_firmware(g, GP104_FECS_UCODE_SIG); 213 fecs_sig = nvgpu_request_firmware(g,
214 GP104_FECS_UCODE_SIG,
215 NVGPU_REQUEST_FIRMWARE_NO_SOC);
210 break; 216 break;
211 case NVGPU_GPUID_GP106: 217 case NVGPU_GPUID_GP106:
212 fecs_sig = gk20a_request_firmware(g, GP106_FECS_UCODE_SIG); 218 fecs_sig = nvgpu_request_firmware(g,
219 GP106_FECS_UCODE_SIG,
220 NVGPU_REQUEST_FIRMWARE_NO_SOC);
213 break; 221 break;
214 default: 222 default:
215 gk20a_err(g->dev, "no support for GPUID %x", ver); 223 gk20a_err(g->dev, "no support for GPUID %x", ver);
@@ -288,10 +296,14 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img)
288 296
289 switch (ver) { 297 switch (ver) {
290 case NVGPU_GPUID_GP104: 298 case NVGPU_GPUID_GP104:
291 gpccs_sig = gk20a_request_firmware(g, GP104_GPCCS_UCODE_SIG); 299 gpccs_sig = nvgpu_request_firmware(g,
300 GP104_GPCCS_UCODE_SIG,
301 NVGPU_REQUEST_FIRMWARE_NO_SOC);
292 break; 302 break;
293 case NVGPU_GPUID_GP106: 303 case NVGPU_GPUID_GP106:
294 gpccs_sig = gk20a_request_firmware(g, GP106_GPCCS_UCODE_SIG); 304 gpccs_sig = nvgpu_request_firmware(g,
305 GP106_GPCCS_UCODE_SIG,
306 NVGPU_REQUEST_FIRMWARE_NO_SOC);
295 break; 307 break;
296 default: 308 default:
297 gk20a_err(g->dev, "no support for GPUID %x", ver); 309 gk20a_err(g->dev, "no support for GPUID %x", ver);
@@ -1041,7 +1053,9 @@ static int gp106_bootstrap_hs_flcn(struct gk20a *g)
1041 1053
1042 if (!acr_fw) { 1054 if (!acr_fw) {
1043 /*First time init case*/ 1055 /*First time init case*/
1044 acr_fw = gk20a_request_firmware(g, GM20B_HSBIN_PMU_UCODE_IMAGE); 1056 acr_fw = nvgpu_request_firmware(g,
1057 GM20B_HSBIN_PMU_UCODE_IMAGE,
1058 NVGPU_REQUEST_FIRMWARE_NO_SOC);
1045 if (!acr_fw) { 1059 if (!acr_fw) {
1046 gk20a_err(dev_from_gk20a(g), "pmu ucode get fail"); 1060 gk20a_err(dev_from_gk20a(g), "pmu ucode get fail");
1047 return -ENOENT; 1061 return -ENOENT;