diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-12-14 17:43:42 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-05 12:13:30 -0500 |
commit | ea5a2147229e32f0524827af82cb7a880aca6296 (patch) | |
tree | 57502c753df7efec4924f9969eb2aebca347c304 /drivers/gpu/nvgpu/gm20b | |
parent | 5711e2b1f7c3a34444c654e7a3bf0a6f8201ef03 (diff) |
gpu: nvgpu: Implement SET_RD_COALESCE
Implement SW method SET_RD_COALESCE to implement correct handling
of texture read coalescing.
Bug 200223870
Change-Id: Icd6f987b72d78e5add4076fc550e2070eba70628
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1271303
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 14 |
3 files changed, 38 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index fc98b5ca..c74b9fec 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -262,6 +262,20 @@ static void gr_gm20b_commit_global_pagepool(struct gk20a *g, | |||
262 | 262 | ||
263 | } | 263 | } |
264 | 264 | ||
265 | void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data) | ||
266 | { | ||
267 | u32 val; | ||
268 | |||
269 | gk20a_dbg_fn(""); | ||
270 | |||
271 | val = gk20a_readl(g, gr_gpcs_tpcs_tex_m_dbg2_r()); | ||
272 | val = set_field(val, gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(), | ||
273 | gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(data)); | ||
274 | gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), val); | ||
275 | |||
276 | gk20a_dbg_fn("done"); | ||
277 | } | ||
278 | |||
265 | static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, | 279 | static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, |
266 | u32 class_num, u32 offset, u32 data) | 280 | u32 class_num, u32 offset, u32 data) |
267 | { | 281 | { |
@@ -272,6 +286,9 @@ static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, | |||
272 | case NVB1C0_SET_SHADER_EXCEPTIONS: | 286 | case NVB1C0_SET_SHADER_EXCEPTIONS: |
273 | gk20a_gr_set_shader_exceptions(g, data); | 287 | gk20a_gr_set_shader_exceptions(g, data); |
274 | break; | 288 | break; |
289 | case NVB1C0_SET_RD_COALESCE: | ||
290 | gr_gm20b_set_rd_coalesce(g, data); | ||
291 | break; | ||
275 | default: | 292 | default: |
276 | goto fail; | 293 | goto fail; |
277 | } | 294 | } |
@@ -288,6 +305,9 @@ static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, | |||
288 | case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE: | 305 | case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE: |
289 | g->ops.gr.set_alpha_circular_buffer_size(g, data); | 306 | g->ops.gr.set_alpha_circular_buffer_size(g, data); |
290 | break; | 307 | break; |
308 | case NVB197_SET_RD_COALESCE: | ||
309 | gr_gm20b_set_rd_coalesce(g, data); | ||
310 | break; | ||
291 | default: | 311 | default: |
292 | goto fail; | 312 | goto fail; |
293 | } | 313 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index a1aef80b..b94259c5 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -39,7 +39,9 @@ enum { | |||
39 | #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc | 39 | #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc |
40 | #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 | 40 | #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 |
41 | #define NVB197_SET_SHADER_EXCEPTIONS 0x1528 | 41 | #define NVB197_SET_SHADER_EXCEPTIONS 0x1528 |
42 | #define NVB197_SET_RD_COALESCE 0x102c | ||
42 | #define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 | 43 | #define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 |
44 | #define NVB1C0_SET_RD_COALESCE 0x0228 | ||
43 | 45 | ||
44 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 46 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
45 | void gm20b_init_gr(struct gpu_ops *gops); | 47 | void gm20b_init_gr(struct gpu_ops *gops); |
@@ -48,5 +50,6 @@ void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, | |||
48 | u64 addr, bool patch); | 50 | u64 addr, bool patch); |
49 | int gr_gm20b_init_fs_state(struct gk20a *g); | 51 | int gr_gm20b_init_fs_state(struct gk20a *g); |
50 | int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask); | 52 | int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask); |
53 | void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data); | ||
51 | 54 | ||
52 | #endif | 55 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 68b5a6d4..9f7fea45 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -2254,6 +2254,18 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) | |||
2254 | { | 2254 | { |
2255 | return 0x005030f8; | 2255 | return 0x005030f8; |
2256 | } | 2256 | } |
2257 | static inline u32 gr_gpcs_tpcs_tex_m_dbg2_r(void) | ||
2258 | { | ||
2259 | return 0x00419a3c; | ||
2260 | } | ||
2261 | static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(u32 v) | ||
2262 | { | ||
2263 | return (v & 0x1) << 2; | ||
2264 | } | ||
2265 | static inline u32 gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(void) | ||
2266 | { | ||
2267 | return 0x1 << 2; | ||
2268 | } | ||
2257 | static inline u32 gr_gpccs_falcon_addr_r(void) | 2269 | static inline u32 gr_gpccs_falcon_addr_r(void) |
2258 | { | 2270 | { |
2259 | return 0x0041a0ac; | 2271 | return 0x0041a0ac; |