diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-22 16:43:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-06 15:04:43 -0400 |
commit | d8c0144f8b45ef8a94fc696efaa0c782c4c787af (patch) | |
tree | 07c7463570e0451731dcd29091e1a254b96cd409 /drivers/gpu/nvgpu/gm20b | |
parent | 0852c9f1aba1654e380ccdd13cd0540fbb5a8ab0 (diff) |
gpu: nvgpu: add clear_sm_hww gr ops
Required for multiple SM support and t19x SM
register address changes
JIRA GPUT19X-75
Change-Id: Iad39f8566e2f5f000b019837304df24d9e2a37e3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514043
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 333f0340..90046232 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1530,6 +1530,18 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr, | |||
1530 | priv_addr_table, priv_addr_table_index); | 1530 | priv_addr_table, priv_addr_table_index); |
1531 | } | 1531 | } |
1532 | 1532 | ||
1533 | static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | ||
1534 | u32 global_esr) | ||
1535 | { | ||
1536 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | ||
1537 | |||
1538 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | ||
1539 | global_esr); | ||
1540 | |||
1541 | /* clear the warp hww */ | ||
1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); | ||
1543 | } | ||
1544 | |||
1533 | void gm20b_init_gr(struct gpu_ops *gops) | 1545 | void gm20b_init_gr(struct gpu_ops *gops) |
1534 | { | 1546 | { |
1535 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 1547 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
@@ -1640,4 +1652,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1640 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask; | 1652 | gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask; |
1641 | gops->gr.lock_down_sm = gk20a_gr_lock_down_sm; | 1653 | gops->gr.lock_down_sm = gk20a_gr_lock_down_sm; |
1642 | gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down; | 1654 | gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down; |
1655 | gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww; | ||
1643 | } | 1656 | } |