diff options
author | Seema Khowala <seemaj@nvidia.com> | 2016-07-08 19:12:44 -0400 |
---|---|---|
committer | Seshendra Gadagottu <sgadagottu@nvidia.com> | 2016-07-27 17:32:54 -0400 |
commit | d64e2015147c4dc48c0d3b8d6ee612dd8addf04c (patch) | |
tree | 68753a49ca7da2264ff007c675b1dfa32f6da3bd /drivers/gpu/nvgpu/gm20b | |
parent | 9ca4c6b596fe50c652907193bb167ee29c208b4b (diff) |
gpu: nvgpu: add check for is_fmodel
is_fmodel flag will be set in gk20a_probe().
Updated code for is_fmodel check, instead of
check for supported simulated platforms.
Bug 1735760
Change-Id: I7cbac2196130fe5ce4c1a910504879e6948c13da
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177869
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 3 |
3 files changed, 7 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index d57b0fb5..c2aa64ba 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -709,10 +709,11 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
709 | u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - | 709 | u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - |
710 | gr_fecs_falcon_hwcfg_r(); | 710 | gr_fecs_falcon_hwcfg_r(); |
711 | u8 falcon_id_mask = 0; | 711 | u8 falcon_id_mask = 0; |
712 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
712 | 713 | ||
713 | gk20a_dbg_fn(""); | 714 | gk20a_dbg_fn(""); |
714 | 715 | ||
715 | if (tegra_platform_is_linsim()) { | 716 | if (platform->is_fmodel) { |
716 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), | 717 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), |
717 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); | 718 | gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); |
718 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), | 719 | gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 57cafd38..caf6a2eb 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -177,11 +177,12 @@ int gm20b_init_hal(struct gk20a *g) | |||
177 | { | 177 | { |
178 | struct gpu_ops *gops = &g->ops; | 178 | struct gpu_ops *gops = &g->ops; |
179 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; | 179 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; |
180 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
180 | 181 | ||
181 | *gops = gm20b_ops; | 182 | *gops = gm20b_ops; |
182 | gops->securegpccs = false; | 183 | gops->securegpccs = false; |
183 | #ifdef CONFIG_TEGRA_ACR | 184 | #ifdef CONFIG_TEGRA_ACR |
184 | if (tegra_platform_is_linsim()) { | 185 | if (platform->is_fmodel) { |
185 | gops->privsecurity = 1; | 186 | gops->privsecurity = 1; |
186 | } else { | 187 | } else { |
187 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & | 188 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & |
@@ -193,7 +194,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
193 | } | 194 | } |
194 | } | 195 | } |
195 | #else | 196 | #else |
196 | if (tegra_platform_is_linsim()) { | 197 | if (platform->is_fmodel) { |
197 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 198 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
198 | gops->privsecurity = 0; | 199 | gops->privsecurity = 0; |
199 | } else { | 200 | } else { |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 56df6a5d..fee9a807 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -48,6 +48,7 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
48 | u32 compbit_backing_size; | 48 | u32 compbit_backing_size; |
49 | 49 | ||
50 | int err; | 50 | int err; |
51 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
51 | 52 | ||
52 | gk20a_dbg_fn(""); | 53 | gk20a_dbg_fn(""); |
53 | 54 | ||
@@ -80,7 +81,7 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
80 | gk20a_dbg_info("max comptag lines : %d", | 81 | gk20a_dbg_info("max comptag lines : %d", |
81 | max_comptag_lines); | 82 | max_comptag_lines); |
82 | 83 | ||
83 | if (tegra_platform_is_linsim()) | 84 | if (platform->is_fmodel) |
84 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); | 85 | err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); |
85 | else | 86 | else |
86 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); | 87 | err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); |