diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-04-10 17:04:15 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-11 09:04:12 -0400 |
commit | c3fa78b1d9cba28547ca59154207d434931ae746 (patch) | |
tree | 42117714f2d8dd217229e6c183d4b6affd29c7d1 /drivers/gpu/nvgpu/gm20b | |
parent | 36c1fdccc994d337fc15dd2b67ff05435f37dec9 (diff) |
gpu: nvgpu: Separate GMMU out of mm_gk20a.c
Begin moving (and renaming) the GMMU code into common/mm/gmmu.c. This
block of code will be responsible for handling the platform/OS
independent GMMU operations.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ide761bab75e5d84be3dcb977c4842ae4b3a7c1b3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464083
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 6679d905..7c56c4cc 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/platform/tegra/mc.h> | 19 | #include <linux/platform/tegra/mc.h> |
20 | 20 | ||
21 | #include <nvgpu/dma.h> | 21 | #include <nvgpu/dma.h> |
22 | #include <nvgpu/gmmu.h> | ||
22 | #include <nvgpu/timers.h> | 23 | #include <nvgpu/timers.h> |
23 | #include <nvgpu/nvgpu_common.h> | 24 | #include <nvgpu/nvgpu_common.h> |
24 | #include <nvgpu/kmem.h> | 25 | #include <nvgpu/kmem.h> |
@@ -413,7 +414,7 @@ int prepare_ucode_blob(struct gk20a *g) | |||
413 | 414 | ||
414 | page = phys_to_page(wpr_addr); | 415 | page = phys_to_page(wpr_addr); |
415 | __nvgpu_mem_create_from_pages(g, &g->pmu.wpr_buf, &page, 1); | 416 | __nvgpu_mem_create_from_pages(g, &g->pmu.wpr_buf, &page, 1); |
416 | g->pmu.wpr_buf.gpu_va = gk20a_gmmu_map(vm, &g->pmu.wpr_buf.priv.sgt, | 417 | g->pmu.wpr_buf.gpu_va = nvgpu_gmmu_map(vm, &g->pmu.wpr_buf, |
417 | wprsize, 0, gk20a_mem_flag_none, | 418 | wprsize, 0, gk20a_mem_flag_none, |
418 | false, APERTURE_SYSMEM); | 419 | false, APERTURE_SYSMEM); |
419 | gm20b_dbg_pmu("wpr mapped gpu va :%llx\n", g->pmu.wpr_buf.gpu_va); | 420 | gm20b_dbg_pmu("wpr mapped gpu va :%llx\n", g->pmu.wpr_buf.gpu_va); |
@@ -445,8 +446,7 @@ int prepare_ucode_blob(struct gk20a *g) | |||
445 | gm20b_dbg_pmu("prepare ucode blob return 0\n"); | 446 | gm20b_dbg_pmu("prepare ucode blob return 0\n"); |
446 | free_acr_resources(g, plsfm); | 447 | free_acr_resources(g, plsfm); |
447 | free_sgt: | 448 | free_sgt: |
448 | gk20a_gmmu_unmap(vm, g->pmu.wpr_buf.gpu_va, | 449 | nvgpu_gmmu_unmap(vm, &g->pmu.wpr_buf, g->pmu.wpr_buf.gpu_va); |
449 | g->pmu.wpr_buf.size, gk20a_mem_flag_none); | ||
450 | return err; | 450 | return err; |
451 | } | 451 | } |
452 | 452 | ||
@@ -1412,8 +1412,8 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1412 | goto err_done; | 1412 | goto err_done; |
1413 | } | 1413 | } |
1414 | 1414 | ||
1415 | acr->hsbl_ucode.gpu_va = gk20a_gmmu_map(vm, | 1415 | acr->hsbl_ucode.gpu_va = nvgpu_gmmu_map(vm, |
1416 | &acr->hsbl_ucode.priv.sgt, | 1416 | &acr->hsbl_ucode, |
1417 | bl_sz, | 1417 | bl_sz, |
1418 | 0, /* flags */ | 1418 | 0, /* flags */ |
1419 | gk20a_mem_flag_read_only, false, | 1419 | gk20a_mem_flag_read_only, false, |
@@ -1461,8 +1461,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1461 | start_gm20b_pmu(g); | 1461 | start_gm20b_pmu(g); |
1462 | return 0; | 1462 | return 0; |
1463 | err_unmap_bl: | 1463 | err_unmap_bl: |
1464 | gk20a_gmmu_unmap(vm, acr->hsbl_ucode.gpu_va, | 1464 | nvgpu_gmmu_unmap(vm, &acr->hsbl_ucode, acr->hsbl_ucode.gpu_va); |
1465 | acr->hsbl_ucode.size, gk20a_mem_flag_none); | ||
1466 | err_free_ucode: | 1465 | err_free_ucode: |
1467 | nvgpu_dma_free(g, &acr->hsbl_ucode); | 1466 | nvgpu_dma_free(g, &acr->hsbl_ucode); |
1468 | err_done: | 1467 | err_done: |