diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-06-20 20:27:02 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-06-21 16:58:07 -0400 |
commit | c3b5b48c0fbecfb874d0fa4aa52286849bb36a5b (patch) | |
tree | 453ae0733cbdf1611a39d04ff50d533fbad31603 /drivers/gpu/nvgpu/gm20b | |
parent | e4e2c1882865163ad53eeaf96acf83802ffbec71 (diff) |
gpu: nvgpu: move slices_per_ltc & cacheline_size init to floorsweeping
It was initialized at .init_comptags, but we may also need them without
comptags.
Jira NVGPUT-63
Change-Id: Ie818c3ecf890fc84323b9662a32d666a6d2b3936
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756373
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 66cd49e7..a8cbca13 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -52,10 +52,6 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
52 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); | 52 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); |
53 | u32 comptags_per_cacheline = | 53 | u32 comptags_per_cacheline = |
54 | ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); | 54 | ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); |
55 | u32 cacheline_size = | ||
56 | 512U << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); | ||
57 | u32 slices_per_ltc = | ||
58 | ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); | ||
59 | 55 | ||
60 | u32 compbit_backing_size; | 56 | u32 compbit_backing_size; |
61 | 57 | ||
@@ -71,7 +67,7 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
71 | 67 | ||
72 | compbit_backing_size = | 68 | compbit_backing_size = |
73 | DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) * | 69 | DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) * |
74 | cacheline_size * slices_per_ltc * g->ltc_count; | 70 | gr->cacheline_size * gr->slices_per_ltc * g->ltc_count; |
75 | 71 | ||
76 | /* aligned to 2KB * ltc_count */ | 72 | /* aligned to 2KB * ltc_count */ |
77 | compbit_backing_size += | 73 | compbit_backing_size += |
@@ -82,7 +78,7 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
82 | 78 | ||
83 | max_comptag_lines = | 79 | max_comptag_lines = |
84 | (compbit_backing_size * comptags_per_cacheline) / | 80 | (compbit_backing_size * comptags_per_cacheline) / |
85 | (cacheline_size * slices_per_ltc * g->ltc_count); | 81 | (gr->cacheline_size * gr->slices_per_ltc * g->ltc_count); |
86 | 82 | ||
87 | if (max_comptag_lines > hw_max_comptag_lines) | 83 | if (max_comptag_lines > hw_max_comptag_lines) |
88 | max_comptag_lines = hw_max_comptag_lines; | 84 | max_comptag_lines = hw_max_comptag_lines; |
@@ -102,8 +98,6 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | |||
102 | 98 | ||
103 | gr->max_comptag_lines = max_comptag_lines; | 99 | gr->max_comptag_lines = max_comptag_lines; |
104 | gr->comptags_per_cacheline = comptags_per_cacheline; | 100 | gr->comptags_per_cacheline = comptags_per_cacheline; |
105 | gr->slices_per_ltc = slices_per_ltc; | ||
106 | gr->cacheline_size = cacheline_size; | ||
107 | 101 | ||
108 | return 0; | 102 | return 0; |
109 | } | 103 | } |
@@ -203,6 +197,7 @@ out: | |||
203 | 197 | ||
204 | void gm20b_ltc_init_fs_state(struct gk20a *g) | 198 | void gm20b_ltc_init_fs_state(struct gk20a *g) |
205 | { | 199 | { |
200 | struct gr_gk20a *gr = &g->gr; | ||
206 | u32 reg; | 201 | u32 reg; |
207 | 202 | ||
208 | nvgpu_log_info(g, "initialize gm20b l2"); | 203 | nvgpu_log_info(g, "initialize gm20b l2"); |
@@ -211,6 +206,11 @@ void gm20b_ltc_init_fs_state(struct gk20a *g) | |||
211 | g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); | 206 | g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); |
212 | nvgpu_log_info(g, "%d ltcs out of %d", g->ltc_count, g->max_ltc_count); | 207 | nvgpu_log_info(g, "%d ltcs out of %d", g->ltc_count, g->max_ltc_count); |
213 | 208 | ||
209 | reg = gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); | ||
210 | gr->slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(reg);; | ||
211 | gr->cacheline_size = | ||
212 | 512U << ltc_ltcs_ltss_cbc_param_cache_line_size_v(reg); | ||
213 | |||
214 | gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), | 214 | gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), |
215 | g->ltc_count); | 215 | g->ltc_count); |
216 | gk20a_writel(g, ltc_ltcs_misc_ltc_num_active_ltcs_r(), | 216 | gk20a_writel(g, ltc_ltcs_misc_ltc_num_active_ltcs_r(), |