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authorSunny He <suhe@nvidia.com>2017-08-01 18:03:26 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-21 16:06:04 -0400
commitb50b379c192714d0d08c3f2d33e90c95cf795253 (patch)
treebd7786d1fec51f168a9393fcb16a8fe56ad25044 /drivers/gpu/nvgpu/gm20b
parent192f1039e11893b9216819837eee871612225849 (diff)
gpu: nvgpu: Move non-fp pmu members from gpu_ops
Move non-function pointer members out of the pmu and pmu_ver substructs of gpu_ops. Ideally gpu_ops will have only function ponters, better matching its intended purpose and improving readability. - g.ops.pmu_ver.cmd_id_zbc_table_update has been changed to g.pmu_ver_cmd_id_zbc_table_update - g.ops.pmu.lspmuwprinitdone has been changed to g.pmu_lsf_pmu_wpr_init_done - g.ops.pmu.lsfloadedfalconid has been changed to g.pmu_lsf_loaded_falcon_id Boolean flags have been implemented using the enabled.h API - g.ops.pmu_ver.is_pmu_zbc_save_supported moved to common flag NVGPU_PMU_ZBC_SAVE - g.ops.pmu.fecsbootstrapdone moved to common flag NVGPU_PMU_FECS_BOOTSTRAP_DONE Jira NVGPU-74 Change-Id: I08fb20f8f382277f2c579f06d561914c000ea6e0 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1530981 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c6
-rw-r--r--drivers/gpu/nvgpu/gm20b/pmu_gm20b.c18
2 files changed, 12 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 56ebc8ca..5fcc3f7b 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -755,8 +755,8 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
755 } 755 }
756 756
757 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; 757 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
758 g->ops.pmu.lsfloadedfalconid = 0; 758 g->pmu_lsf_loaded_falcon_id = 0;
759 if (g->ops.pmu.fecsbootstrapdone) { 759 if (nvgpu_is_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE)) {
760 /* this must be recovery so bootstrap fecs and gpccs */ 760 /* this must be recovery so bootstrap fecs and gpccs */
761 if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { 761 if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
762 gr_gm20b_load_gpccs_with_bootloader(g); 762 gr_gm20b_load_gpccs_with_bootloader(g);
@@ -776,7 +776,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
776 776
777 } else { 777 } else {
778 /* cold boot or rg exit */ 778 /* cold boot or rg exit */
779 g->ops.pmu.fecsbootstrapdone = true; 779 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, true);
780 if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { 780 if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) {
781 gr_gm20b_load_gpccs_with_bootloader(g); 781 gr_gm20b_load_gpccs_with_bootloader(g);
782 } else { 782 } else {
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index b85e72a0..a5940fcf 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -132,7 +132,7 @@ static void pmu_handle_acr_init_wpr_msg(struct gk20a *g, struct pmu_msg *msg,
132 gm20b_dbg_pmu("reply PMU_ACR_CMD_ID_INIT_WPR_REGION"); 132 gm20b_dbg_pmu("reply PMU_ACR_CMD_ID_INIT_WPR_REGION");
133 133
134 if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) 134 if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS)
135 g->ops.pmu.lspmuwprinitdone = 1; 135 g->pmu_lsf_pmu_wpr_init_done = 1;
136 gk20a_dbg_fn("done"); 136 gk20a_dbg_fn("done");
137} 137}
138 138
@@ -171,7 +171,7 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
171 gm20b_dbg_pmu("reply PMU_ACR_CMD_ID_BOOTSTRAP_FALCON"); 171 gm20b_dbg_pmu("reply PMU_ACR_CMD_ID_BOOTSTRAP_FALCON");
172 172
173 gm20b_dbg_pmu("response code = %x\n", msg->msg.acr.acrmsg.falconid); 173 gm20b_dbg_pmu("response code = %x\n", msg->msg.acr.acrmsg.falconid);
174 g->ops.pmu.lsfloadedfalconid = msg->msg.acr.acrmsg.falconid; 174 g->pmu_lsf_loaded_falcon_id = msg->msg.acr.acrmsg.falconid;
175 gk20a_dbg_fn("done"); 175 gk20a_dbg_fn("done");
176} 176}
177 177
@@ -205,8 +205,8 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags)
205 205
206 gk20a_dbg_fn(""); 206 gk20a_dbg_fn("");
207 207
208 gm20b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); 208 gm20b_dbg_pmu("wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done);
209 if (g->ops.pmu.lspmuwprinitdone) { 209 if (g->pmu_lsf_pmu_wpr_init_done) {
210 /* send message to load FECS falcon */ 210 /* send message to load FECS falcon */
211 memset(&cmd, 0, sizeof(struct pmu_cmd)); 211 memset(&cmd, 0, sizeof(struct pmu_cmd));
212 cmd.hdr.unit_id = PMU_UNIT_ACR; 212 cmd.hdr.unit_id = PMU_UNIT_ACR;
@@ -236,12 +236,12 @@ static int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
236 if (!(falconidmask == (1 << LSF_FALCON_ID_FECS))) 236 if (!(falconidmask == (1 << LSF_FALCON_ID_FECS)))
237 return -EINVAL; 237 return -EINVAL;
238 /* check whether pmu is ready to bootstrap lsf if not wait for it */ 238 /* check whether pmu is ready to bootstrap lsf if not wait for it */
239 if (!g->ops.pmu.lspmuwprinitdone) { 239 if (!g->pmu_lsf_pmu_wpr_init_done) {
240 pmu_wait_message_cond(&g->pmu, 240 pmu_wait_message_cond(&g->pmu,
241 gk20a_get_gr_idle_timeout(g), 241 gk20a_get_gr_idle_timeout(g),
242 &g->ops.pmu.lspmuwprinitdone, 1); 242 &g->pmu_lsf_pmu_wpr_init_done, 1);
243 /* check again if it still not ready indicate an error */ 243 /* check again if it still not ready indicate an error */
244 if (!g->ops.pmu.lspmuwprinitdone) { 244 if (!g->pmu_lsf_pmu_wpr_init_done) {
245 nvgpu_err(g, "PMU not ready to load LSF"); 245 nvgpu_err(g, "PMU not ready to load LSF");
246 return -ETIMEDOUT; 246 return -ETIMEDOUT;
247 } 247 }
@@ -299,8 +299,8 @@ void gm20b_init_pmu_ops(struct gk20a *g)
299 gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; 299 gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v;
300 gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; 300 gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire;
301 gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; 301 gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release;
302 gops->pmu.lspmuwprinitdone = 0; 302 g->pmu_lsf_pmu_wpr_init_done = 0;
303 gops->pmu.fecsbootstrapdone = false; 303 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
304 gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; 304 gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase;
305 gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; 305 gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics;
306 gops->pmu.pmu_pg_init_param = NULL; 306 gops->pmu.pmu_pg_init_param = NULL;