gpu: nvgpu: Use debug sig for NVDEC if on dbg SKU

Debug fused chips do not have production signature. Use debug
signature for memory unlock binary. Requires also exporting a HAL
for checking debug mode from PMU.

Bug 200445202

Change-Id: I7f88ed6db2fe1c614fe9d4074dbf974c3817f453
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809225
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 9 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 9725ebe7..24112dd3 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1141,12 +1141,6 @@ err_release_acr_fw:
         return err;
 }
 
-static u8 pmu_is_debug_mode_en(struct gk20a *g)
-{
-        u32 ctl_stat =  gk20a_readl(g, pwr_pmu_scpctl_stat_r());
-        return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat);
-}
-
 /*
  * @brief Patch signatures into ucode image
  */
@@ -1160,7 +1154,7 @@ int acr_ucode_patch_sig(struct gk20a *g,
         unsigned int i, *p_sig;
         nvgpu_pmu_dbg(g, " ");
 
-        if (!pmu_is_debug_mode_en(g)) {
+        if (!g->ops.pmu.is_debug_mode_enabled(g)) {
                 p_sig = p_prod_sig;
                 nvgpu_pmu_dbg(g, "PRODUCTION MODE\n");
         } else {
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 835d18d4..a2b23cca 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -550,6 +550,7 @@ static const struct gpu_ops gm20b_ops = {
                 .reset_engine = gk20a_pmu_engine_reset,
                 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
                 .get_irqdest = gk20a_pmu_get_irqdest,
+                .is_debug_mode_enabled = gm20b_pmu_is_debug_mode_en,
         },
         .clk = {
                 .init_clk_support = gm20b_init_clk_support,
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 38970f73..a46f8807 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -271,3 +271,9 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g)
         nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val);
         nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
 }
+
+bool gm20b_pmu_is_debug_mode_en(struct gk20a *g)
+{
+        u32 ctl_stat =  gk20a_readl(g, pwr_pmu_scpctl_stat_r());
+        return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U;
+}
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
index ec50fb06..1923c047 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
@@ -33,5 +33,6 @@ void pmu_dump_security_fuses_gm20b(struct gk20a *g);
 void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags);
 int gm20b_pmu_init_acr(struct gk20a *g);
 void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);
+bool gm20b_pmu_is_debug_mode_en(struct gk20a *g);
 
 #endif /*__PMU_GM20B_H_*/