diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-04-06 06:37:28 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-04-10 14:23:14 -0400 |
commit | aa1f8e01ced661b640ee612f6a7bd201f0bbd6a4 (patch) | |
tree | 470c04c8fe4ba504da87db51fcd83752cedad3a9 /drivers/gpu/nvgpu/gm20b | |
parent | 78151bb6f9cf9f355c57a28df0c7e4cd867c3322 (diff) |
gpu: nvgpu: fix fpb_en_mask
In gr_gm20b_get_fbp_en_mask(), we read incorrect fuse register to get status
of enabled FBPs
And then we use incorrect arithmetic to calculate fpb_en_mask
Fix this by using correct fuse register and also doing correct arithmetic to get
mask of enabled FBPs
Bug 200398811
Jira NVGPU-556
Change-Id: I79f3ebf590faa9baf176c7a939142c379bf5ebf4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1690029
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 262957c5..1c966c22 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1073,16 +1073,22 @@ int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, | |||
1073 | 1073 | ||
1074 | u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g) | 1074 | u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g) |
1075 | { | 1075 | { |
1076 | u32 fbp_en_mask, opt_fbio; | 1076 | u32 fbp_en_mask; |
1077 | u32 tmp, max_fbps_count; | 1077 | u32 tmp, max_fbps_count; |
1078 | 1078 | ||
1079 | tmp = gk20a_readl(g, top_num_fbps_r()); | 1079 | tmp = gk20a_readl(g, top_num_fbps_r()); |
1080 | max_fbps_count = top_num_fbps_value_v(tmp); | 1080 | max_fbps_count = top_num_fbps_value_v(tmp); |
1081 | 1081 | ||
1082 | opt_fbio = gk20a_readl(g, fuse_status_opt_fbio_r()); | 1082 | /* |
1083 | fbp_en_mask = | 1083 | * Read active fbp mask from fuse |
1084 | ((1 << max_fbps_count) - 1) ^ | 1084 | * Note that 0:enable and 1:disable in value read from fuse so we've to |
1085 | fuse_status_opt_fbio_data_v(opt_fbio); | 1085 | * flip the bits. |
1086 | * Also set unused bits to zero | ||
1087 | */ | ||
1088 | fbp_en_mask = gk20a_readl(g, fuse_status_opt_fbp_r()); | ||
1089 | fbp_en_mask = ~fbp_en_mask; | ||
1090 | fbp_en_mask = fbp_en_mask & ((1 << max_fbps_count) - 1); | ||
1091 | |||
1086 | return fbp_en_mask; | 1092 | return fbp_en_mask; |
1087 | } | 1093 | } |
1088 | 1094 | ||