diff options
author | Bo Yan <byan@nvidia.com> | 2014-04-14 15:03:27 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:09:38 -0400 |
commit | 9eb1f57ba2b7072c6c53ca9dc59b10a87d88db23 (patch) | |
tree | de095fcbae617e938064e45a96b4e176015fe773 /drivers/gpu/nvgpu/gm20b | |
parent | 2531751f53fc21bdeb0ece4af550ea1e8efb9653 (diff) |
gpu: nvgpu: Add GPU driver for GM20B
this moves GM20B driver to the new location
Change-Id: I5fde14e114a8db79738a4c61849912b1ae225fb5
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
32 files changed, 10153 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/Makefile b/drivers/gpu/nvgpu/gm20b/Makefile new file mode 100644 index 00000000..42c3cec0 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/Makefile | |||
@@ -0,0 +1,11 @@ | |||
1 | GCOV_PROFILE := y | ||
2 | ccflags-y += -Idrivers/gpu/nvgpu | ||
3 | ccflags-y += -Wno-multichar | ||
4 | |||
5 | obj-$(CONFIG_GK20A) = \ | ||
6 | hal_gm20b.o \ | ||
7 | ltc_gm20b.o \ | ||
8 | gr_gm20b.o \ | ||
9 | gr_gm20b.o \ | ||
10 | fb_gm20b.o \ | ||
11 | gm20b_gating_reglist.o | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c new file mode 100644 index 00000000..6df3d401 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c | |||
@@ -0,0 +1,89 @@ | |||
1 | /* | ||
2 | * GM20B GPC MMU | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | #include "gk20a/gk20a.h" | ||
19 | #include "gk20a/kind_gk20a.h" | ||
20 | |||
21 | #include "hw_fb_gm20b.h" | ||
22 | #include "hw_top_gm20b.h" | ||
23 | #include "hw_gmmu_gm20b.h" | ||
24 | |||
25 | static void fb_gm20b_init_fs_state(struct gk20a *g) | ||
26 | { | ||
27 | gk20a_dbg_info("initialize gm20b fb"); | ||
28 | |||
29 | gk20a_writel(g, fb_fbhub_num_active_ltcs_r(), | ||
30 | g->ltc_count); | ||
31 | } | ||
32 | |||
33 | static void gm20b_init_uncompressed_kind_map(void) | ||
34 | { | ||
35 | gk20a_init_uncompressed_kind_map(); | ||
36 | |||
37 | gk20a_uc_kind_map[gmmu_pte_kind_s8_v()] = | ||
38 | gk20a_uc_kind_map[gmmu_pte_kind_s8_2s_v()] = | ||
39 | gmmu_pte_kind_s8_v(); | ||
40 | } | ||
41 | |||
42 | static bool gm20b_kind_supported(u8 k) | ||
43 | { | ||
44 | return (k >= gmmu_pte_kind_s8_v() && | ||
45 | k <= gmmu_pte_kind_s8_2s_v()); | ||
46 | } | ||
47 | |||
48 | static bool gm20b_kind_z(u8 k) | ||
49 | { | ||
50 | return (k >= gmmu_pte_kind_s8_v() && | ||
51 | k <= gmmu_pte_kind_s8_2s_v()); | ||
52 | } | ||
53 | |||
54 | static bool gm20b_kind_compressible(u8 k) | ||
55 | { | ||
56 | return (k >= gmmu_pte_kind_s8_v() && | ||
57 | k <= gmmu_pte_kind_s8_2s_v()); | ||
58 | } | ||
59 | |||
60 | static bool gm20b_kind_zbc(u8 k) | ||
61 | { | ||
62 | return (k >= gmmu_pte_kind_s8_v() && | ||
63 | k <= gmmu_pte_kind_s8_2s_v()); | ||
64 | } | ||
65 | |||
66 | void gm20b_init_kind_attr(void) | ||
67 | { | ||
68 | u16 k; | ||
69 | |||
70 | gk20a_init_kind_attr(); | ||
71 | |||
72 | for (k = 0; k < 256; k++) { | ||
73 | if (gm20b_kind_supported((u8)k)) | ||
74 | gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; | ||
75 | if (gm20b_kind_compressible((u8)k)) | ||
76 | gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; | ||
77 | if (gm20b_kind_z((u8)k)) | ||
78 | gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; | ||
79 | if (gm20b_kind_zbc((u8)k)) | ||
80 | gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; | ||
81 | } | ||
82 | } | ||
83 | |||
84 | void gm20b_init_fb(struct gpu_ops *gops) | ||
85 | { | ||
86 | gops->fb.init_fs_state = fb_gm20b_init_fs_state; | ||
87 | gm20b_init_uncompressed_kind_map(); | ||
88 | gm20b_init_kind_attr(); | ||
89 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h new file mode 100644 index 00000000..4d48d797 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * GM20B FB | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVHOST_GM20B_FB | ||
17 | #define _NVHOST_GM20B_FB | ||
18 | struct gk20a; | ||
19 | |||
20 | void gm20b_init_fb(struct gpu_ops *gops); | ||
21 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c new file mode 100644 index 00000000..6b8648d3 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.c | |||
@@ -0,0 +1,254 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gm20b/gm20b_gating_reglist.c | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along | ||
16 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
18 | * | ||
19 | * This file is autogenerated. Do not edit. | ||
20 | */ | ||
21 | |||
22 | #ifndef __gm20b_gating_reglist_h__ | ||
23 | #define __gm20b_gating_reglist_h__ | ||
24 | |||
25 | #include <linux/types.h> | ||
26 | |||
27 | #include "gm20b_gating_reglist.h" | ||
28 | |||
29 | struct gating_desc { | ||
30 | u32 addr; | ||
31 | u32 prod; | ||
32 | u32 disable; | ||
33 | }; | ||
34 | /* slcg gr */ | ||
35 | const struct gating_desc gm20b_slcg_gr[] = { | ||
36 | {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x03fffffe}, | ||
37 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
38 | {.addr = 0x00409894, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
39 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | ||
40 | {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
41 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | ||
42 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
43 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | ||
44 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x0000007e}, | ||
45 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | ||
46 | {.addr = 0x0041a894, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
47 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | ||
48 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
49 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | ||
50 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
51 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | ||
52 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
53 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | ||
54 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
55 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | ||
56 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | ||
57 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
58 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | ||
59 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
60 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | ||
61 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
62 | {.addr = 0x00419d64, .prod = 0x00000000, .disable = 0x000001ff}, | ||
63 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | ||
64 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | ||
65 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | ||
66 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
67 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | ||
68 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | ||
69 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | ||
70 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | ||
71 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | ||
72 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | ||
73 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
74 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | ||
75 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | ||
76 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | ||
77 | {.addr = 0x00419fdc, .prod = 0xfffffffe, .disable = 0xfffffffe}, | ||
78 | {.addr = 0x00419fe4, .prod = 0x00000000, .disable = 0x00001ffe}, | ||
79 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | ||
80 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
81 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | ||
82 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | ||
83 | {.addr = 0x0041bed4, .prod = 0xfffffff6, .disable = 0xfffffffe}, | ||
84 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
85 | {.addr = 0x0040881c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
86 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
87 | {.addr = 0x00408a8c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
88 | {.addr = 0x00408a94, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
89 | {.addr = 0x00408a9c, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
90 | {.addr = 0x00408aa4, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
91 | {.addr = 0x00408aac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
92 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | ||
93 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x000001ff}, | ||
94 | }; | ||
95 | |||
96 | /* slcg perf */ | ||
97 | const struct gating_desc gm20b_slcg_perf[] = { | ||
98 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
99 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
100 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | ||
101 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | ||
102 | }; | ||
103 | |||
104 | /* blcg gr */ | ||
105 | const struct gating_desc gm20b_blcg_gr[] = { | ||
106 | {.addr = 0x004041f0, .prod = 0x00004046, .disable = 0x00000000}, | ||
107 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
108 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
109 | {.addr = 0x004078c0, .prod = 0x00000042, .disable = 0x00000000}, | ||
110 | {.addr = 0x00406000, .prod = 0x00004044, .disable = 0x00000000}, | ||
111 | {.addr = 0x00405860, .prod = 0x00004042, .disable = 0x00000000}, | ||
112 | {.addr = 0x0040590c, .prod = 0x00004044, .disable = 0x00000000}, | ||
113 | {.addr = 0x00408040, .prod = 0x00004044, .disable = 0x00000000}, | ||
114 | {.addr = 0x00407000, .prod = 0x00004041, .disable = 0x00000000}, | ||
115 | {.addr = 0x00405bf0, .prod = 0x00004044, .disable = 0x00000000}, | ||
116 | {.addr = 0x0041a890, .prod = 0x0000007f, .disable = 0x00000000}, | ||
117 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | ||
118 | {.addr = 0x00418500, .prod = 0x00004044, .disable = 0x00000000}, | ||
119 | {.addr = 0x00418608, .prod = 0x00004042, .disable = 0x00000000}, | ||
120 | {.addr = 0x00418688, .prod = 0x00004042, .disable = 0x00000000}, | ||
121 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | ||
122 | {.addr = 0x00418828, .prod = 0x00000044, .disable = 0x00000000}, | ||
123 | {.addr = 0x00418bbc, .prod = 0x00004042, .disable = 0x00000000}, | ||
124 | {.addr = 0x00418970, .prod = 0x00004042, .disable = 0x00000000}, | ||
125 | {.addr = 0x00418c70, .prod = 0x00004044, .disable = 0x00000000}, | ||
126 | {.addr = 0x00418cf0, .prod = 0x00004044, .disable = 0x00000000}, | ||
127 | {.addr = 0x00418d70, .prod = 0x00004044, .disable = 0x00000000}, | ||
128 | {.addr = 0x00418f0c, .prod = 0x00004044, .disable = 0x00000000}, | ||
129 | {.addr = 0x00418e0c, .prod = 0x00004044, .disable = 0x00000000}, | ||
130 | {.addr = 0x00419020, .prod = 0x00004042, .disable = 0x00000000}, | ||
131 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | ||
132 | {.addr = 0x00418898, .prod = 0x00000042, .disable = 0x00000000}, | ||
133 | {.addr = 0x00419a40, .prod = 0x00004042, .disable = 0x00000000}, | ||
134 | {.addr = 0x00419a48, .prod = 0x00004042, .disable = 0x00000000}, | ||
135 | {.addr = 0x00419a50, .prod = 0x00004042, .disable = 0x00000000}, | ||
136 | {.addr = 0x00419a58, .prod = 0x00004042, .disable = 0x00000000}, | ||
137 | {.addr = 0x00419a60, .prod = 0x00004042, .disable = 0x00000000}, | ||
138 | {.addr = 0x00419a68, .prod = 0x00004042, .disable = 0x00000000}, | ||
139 | {.addr = 0x00419a70, .prod = 0x00004042, .disable = 0x00000000}, | ||
140 | {.addr = 0x00419a78, .prod = 0x00004042, .disable = 0x00000000}, | ||
141 | {.addr = 0x00419a80, .prod = 0x00004042, .disable = 0x00000000}, | ||
142 | {.addr = 0x00419868, .prod = 0x00000042, .disable = 0x00000000}, | ||
143 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | ||
144 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | ||
145 | {.addr = 0x00419c70, .prod = 0x00004044, .disable = 0x00000000}, | ||
146 | {.addr = 0x00419fd0, .prod = 0x00000044, .disable = 0x00000000}, | ||
147 | {.addr = 0x00419fd8, .prod = 0x00000045, .disable = 0x00000000}, | ||
148 | {.addr = 0x00419fe0, .prod = 0x00000044, .disable = 0x00000000}, | ||
149 | {.addr = 0x00419fe8, .prod = 0x00000042, .disable = 0x00000000}, | ||
150 | {.addr = 0x00419ff0, .prod = 0x00000045, .disable = 0x00000000}, | ||
151 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | ||
152 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | ||
153 | {.addr = 0x0041be28, .prod = 0x00000042, .disable = 0x00000000}, | ||
154 | {.addr = 0x0041bfe8, .prod = 0x00004044, .disable = 0x00000000}, | ||
155 | {.addr = 0x0041bed0, .prod = 0x00004044, .disable = 0x00000000}, | ||
156 | {.addr = 0x00408810, .prod = 0x00004042, .disable = 0x00000000}, | ||
157 | {.addr = 0x00408818, .prod = 0x00004042, .disable = 0x00000000}, | ||
158 | {.addr = 0x00408a80, .prod = 0x00004042, .disable = 0x00000000}, | ||
159 | {.addr = 0x00408a88, .prod = 0x00004042, .disable = 0x00000000}, | ||
160 | {.addr = 0x00408a90, .prod = 0x00004042, .disable = 0x00000000}, | ||
161 | {.addr = 0x00408a98, .prod = 0x00004042, .disable = 0x00000000}, | ||
162 | {.addr = 0x00408aa0, .prod = 0x00004042, .disable = 0x00000000}, | ||
163 | {.addr = 0x00408aa8, .prod = 0x00004042, .disable = 0x00000000}, | ||
164 | {.addr = 0x004089a8, .prod = 0x00004042, .disable = 0x00000000}, | ||
165 | {.addr = 0x004089b0, .prod = 0x00000042, .disable = 0x00000000}, | ||
166 | {.addr = 0x004089b8, .prod = 0x00004042, .disable = 0x00000000}, | ||
167 | }; | ||
168 | |||
169 | /* pg gr */ | ||
170 | const struct gating_desc gm20b_pg_gr[] = { | ||
171 | }; | ||
172 | |||
173 | /* therm gr */ | ||
174 | const struct gating_desc gm20b_slcg_therm[] = { | ||
175 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | ||
176 | }; | ||
177 | |||
178 | /* static inline functions */ | ||
179 | void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
180 | bool prod) | ||
181 | { | ||
182 | u32 i; | ||
183 | u32 size = sizeof(gm20b_slcg_gr) / sizeof(struct gating_desc); | ||
184 | for (i = 0; i < size; i++) { | ||
185 | if (prod) | ||
186 | gk20a_writel(g, gm20b_slcg_gr[i].addr, | ||
187 | gm20b_slcg_gr[i].prod); | ||
188 | else | ||
189 | gk20a_writel(g, gm20b_slcg_gr[i].addr, | ||
190 | gm20b_slcg_gr[i].disable); | ||
191 | } | ||
192 | } | ||
193 | |||
194 | void gr_gm20b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
195 | bool prod) | ||
196 | { | ||
197 | u32 i; | ||
198 | u32 size = sizeof(gm20b_slcg_perf) / sizeof(struct gating_desc); | ||
199 | for (i = 0; i < size; i++) { | ||
200 | if (prod) | ||
201 | gk20a_writel(g, gm20b_slcg_perf[i].addr, | ||
202 | gm20b_slcg_perf[i].prod); | ||
203 | else | ||
204 | gk20a_writel(g, gm20b_slcg_perf[i].addr, | ||
205 | gm20b_slcg_perf[i].disable); | ||
206 | } | ||
207 | } | ||
208 | |||
209 | void gr_gm20b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
210 | bool prod) | ||
211 | { | ||
212 | u32 i; | ||
213 | u32 size = sizeof(gm20b_blcg_gr) / sizeof(struct gating_desc); | ||
214 | for (i = 0; i < size; i++) { | ||
215 | if (prod) | ||
216 | gk20a_writel(g, gm20b_blcg_gr[i].addr, | ||
217 | gm20b_blcg_gr[i].prod); | ||
218 | else | ||
219 | gk20a_writel(g, gm20b_blcg_gr[i].addr, | ||
220 | gm20b_blcg_gr[i].disable); | ||
221 | } | ||
222 | } | ||
223 | |||
224 | void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, | ||
225 | bool prod) | ||
226 | { | ||
227 | u32 i; | ||
228 | u32 size = sizeof(gm20b_pg_gr) / sizeof(struct gating_desc); | ||
229 | for (i = 0; i < size; i++) { | ||
230 | if (prod) | ||
231 | gk20a_writel(g, gm20b_pg_gr[i].addr, | ||
232 | gm20b_pg_gr[i].prod); | ||
233 | else | ||
234 | gk20a_writel(g, gm20b_pg_gr[i].addr, | ||
235 | gm20b_pg_gr[i].disable); | ||
236 | } | ||
237 | } | ||
238 | |||
239 | void gr_gm20b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
240 | bool prod) | ||
241 | { | ||
242 | u32 i; | ||
243 | u32 size = sizeof(gm20b_slcg_therm) / sizeof(struct gating_desc); | ||
244 | for (i = 0; i < size; i++) { | ||
245 | if (prod) | ||
246 | gk20a_writel(g, gm20b_slcg_therm[i].addr, | ||
247 | gm20b_slcg_therm[i].prod); | ||
248 | else | ||
249 | gk20a_writel(g, gm20b_slcg_therm[i].addr, | ||
250 | gm20b_slcg_therm[i].disable); | ||
251 | } | ||
252 | } | ||
253 | |||
254 | #endif /* __gm20b_gating_reglist_h__ */ | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h new file mode 100644 index 00000000..4097fad2 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/gm20b_gating_reglist.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gm20b/gm20b_gating_reglist.h | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along | ||
16 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. | ||
18 | * | ||
19 | * This file is autogenerated. Do not edit. | ||
20 | */ | ||
21 | |||
22 | #include "gk20a/gk20a.h" | ||
23 | |||
24 | void gr_gm20b_slcg_gr_load_gating_prod(struct gk20a *g, | ||
25 | bool prod); | ||
26 | |||
27 | void gr_gm20b_slcg_perf_load_gating_prod(struct gk20a *g, | ||
28 | bool prod); | ||
29 | |||
30 | void gr_gm20b_blcg_gr_load_gating_prod(struct gk20a *g, | ||
31 | bool prod); | ||
32 | |||
33 | void gr_gm20b_pg_gr_load_gating_prod(struct gk20a *g, | ||
34 | bool prod); | ||
35 | |||
36 | void gr_gm20b_slcg_therm_load_gating_prod(struct gk20a *g, | ||
37 | bool prod); | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c new file mode 100644 index 00000000..54184766 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -0,0 +1,593 @@ | |||
1 | /* | ||
2 | * GM20B GPC MMU | ||
3 | * | ||
4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | #include "gk20a/gk20a.h" | ||
19 | #include "gk20a/gr_gk20a.h" | ||
20 | |||
21 | #include "gr_gm20b.h" | ||
22 | #include "hw_gr_gm20b.h" | ||
23 | #include "hw_fb_gm20b.h" | ||
24 | #include "hw_proj_gm20b.h" | ||
25 | #include "hw_ctxsw_prog_gm20b.h" | ||
26 | |||
27 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | ||
28 | { | ||
29 | u32 temp; | ||
30 | |||
31 | gk20a_dbg_info("initialize gpc mmu"); | ||
32 | |||
33 | temp = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
34 | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | | ||
35 | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | | ||
36 | gr_gpcs_pri_mmu_ctrl_vol_fault_m() | | ||
37 | gr_gpcs_pri_mmu_ctrl_comp_fault_m() | | ||
38 | gr_gpcs_pri_mmu_ctrl_miss_gran_m() | | ||
39 | gr_gpcs_pri_mmu_ctrl_cache_mode_m() | | ||
40 | gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() | | ||
41 | gr_gpcs_pri_mmu_ctrl_mmu_vol_m() | | ||
42 | gr_gpcs_pri_mmu_ctrl_mmu_disable_m(); | ||
43 | gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp); | ||
44 | gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0); | ||
45 | gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); | ||
46 | |||
47 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), | ||
48 | gk20a_readl(g, fb_mmu_debug_ctrl_r())); | ||
49 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), | ||
50 | gk20a_readl(g, fb_mmu_debug_wr_r())); | ||
51 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), | ||
52 | gk20a_readl(g, fb_mmu_debug_rd_r())); | ||
53 | |||
54 | gk20a_writel(g, gr_gpcs_mmu_num_active_ltcs_r(), | ||
55 | gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); | ||
56 | } | ||
57 | |||
58 | static void gr_gm20b_bundle_cb_defaults(struct gk20a *g) | ||
59 | { | ||
60 | struct gr_gk20a *gr = &g->gr; | ||
61 | |||
62 | gr->bundle_cb_default_size = | ||
63 | gr_scc_bundle_cb_size_div_256b__prod_v(); | ||
64 | gr->min_gpm_fifo_depth = | ||
65 | gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(); | ||
66 | gr->bundle_cb_token_limit = | ||
67 | gr_pd_ab_dist_cfg2_token_limit_init_v(); | ||
68 | } | ||
69 | |||
70 | static void gr_gm20b_cb_size_default(struct gk20a *g) | ||
71 | { | ||
72 | struct gr_gk20a *gr = &g->gr; | ||
73 | |||
74 | gr->attrib_cb_default_size = | ||
75 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); | ||
76 | gr->alpha_cb_default_size = | ||
77 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); | ||
78 | } | ||
79 | |||
80 | static int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) | ||
81 | { | ||
82 | struct gr_gk20a *gr = &g->gr; | ||
83 | int size; | ||
84 | |||
85 | gr->attrib_cb_size = gr->attrib_cb_default_size | ||
86 | + (gr->attrib_cb_default_size >> 1); | ||
87 | gr->alpha_cb_size = gr->alpha_cb_default_size | ||
88 | + (gr->alpha_cb_default_size >> 1); | ||
89 | |||
90 | size = gr->attrib_cb_size * | ||
91 | gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * | ||
92 | gr->max_tpc_count; | ||
93 | |||
94 | size += gr->alpha_cb_size * | ||
95 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() * | ||
96 | gr->max_tpc_count; | ||
97 | |||
98 | return size; | ||
99 | } | ||
100 | |||
101 | static void gr_gk20a_commit_global_attrib_cb(struct gk20a *g, | ||
102 | struct channel_ctx_gk20a *ch_ctx, | ||
103 | u64 addr, bool patch) | ||
104 | { | ||
105 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_setup_attrib_cb_base_r(), | ||
106 | gr_gpcs_setup_attrib_cb_base_addr_39_12_f(addr) | | ||
107 | gr_gpcs_setup_attrib_cb_base_valid_true_f(), patch); | ||
108 | |||
109 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(), | ||
110 | gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(addr) | | ||
111 | gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(), patch); | ||
112 | |||
113 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(), | ||
114 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) | | ||
115 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); | ||
116 | } | ||
117 | |||
118 | static void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, | ||
119 | struct channel_ctx_gk20a *ch_ctx, | ||
120 | u64 addr, u64 size, bool patch) | ||
121 | { | ||
122 | u32 data; | ||
123 | |||
124 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_base_r(), | ||
125 | gr_scc_bundle_cb_base_addr_39_8_f(addr), patch); | ||
126 | |||
127 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_size_r(), | ||
128 | gr_scc_bundle_cb_size_div_256b_f(size) | | ||
129 | gr_scc_bundle_cb_size_valid_true_f(), patch); | ||
130 | |||
131 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_base_r(), | ||
132 | gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(addr), patch); | ||
133 | |||
134 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_size_r(), | ||
135 | gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) | | ||
136 | gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch); | ||
137 | |||
138 | /* data for state_limit */ | ||
139 | data = (g->gr.bundle_cb_default_size * | ||
140 | gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) / | ||
141 | gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(); | ||
142 | |||
143 | data = min_t(u32, data, g->gr.min_gpm_fifo_depth); | ||
144 | |||
145 | gk20a_dbg_info("bundle cb token limit : %d, state limit : %d", | ||
146 | g->gr.bundle_cb_token_limit, data); | ||
147 | |||
148 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(), | ||
149 | gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) | | ||
150 | gr_pd_ab_dist_cfg2_state_limit_f(data), patch); | ||
151 | |||
152 | } | ||
153 | |||
154 | static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, | ||
155 | struct channel_gk20a *c, bool patch) | ||
156 | { | ||
157 | struct gr_gk20a *gr = &g->gr; | ||
158 | struct channel_ctx_gk20a *ch_ctx = NULL; | ||
159 | u32 attrib_offset_in_chunk = 0; | ||
160 | u32 alpha_offset_in_chunk = 0; | ||
161 | u32 pd_ab_max_output; | ||
162 | u32 gpc_index, ppc_index; | ||
163 | u32 temp; | ||
164 | u32 cbm_cfg_size1, cbm_cfg_size2; | ||
165 | |||
166 | gk20a_dbg_fn(""); | ||
167 | |||
168 | if (patch) { | ||
169 | int err; | ||
170 | ch_ctx = &c->ch_ctx; | ||
171 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | ||
172 | if (err) | ||
173 | return err; | ||
174 | } | ||
175 | |||
176 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_r(), | ||
177 | gr_ds_tga_constraintlogic_beta_cbsize_f(gr->attrib_cb_default_size) | | ||
178 | gr_ds_tga_constraintlogic_alpha_cbsize_f(gr->alpha_cb_default_size), | ||
179 | patch); | ||
180 | |||
181 | pd_ab_max_output = (gr->alpha_cb_default_size * | ||
182 | gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) / | ||
183 | gr_pd_ab_dist_cfg1_max_output_granularity_v(); | ||
184 | |||
185 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(), | ||
186 | gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | | ||
187 | gr_pd_ab_dist_cfg1_max_batches_init_f(), patch); | ||
188 | |||
189 | alpha_offset_in_chunk = attrib_offset_in_chunk + | ||
190 | gr->tpc_count * gr->attrib_cb_size; | ||
191 | |||
192 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
193 | temp = proj_gpc_stride_v() * gpc_index; | ||
194 | for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; | ||
195 | ppc_index++) { | ||
196 | cbm_cfg_size1 = gr->attrib_cb_default_size * | ||
197 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
198 | cbm_cfg_size2 = gr->alpha_cb_default_size * | ||
199 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
200 | |||
201 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
202 | gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + | ||
203 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
204 | cbm_cfg_size1, patch); | ||
205 | |||
206 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
207 | gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + | ||
208 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
209 | attrib_offset_in_chunk, patch); | ||
210 | |||
211 | attrib_offset_in_chunk += gr->attrib_cb_size * | ||
212 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
213 | |||
214 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
215 | gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + | ||
216 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
217 | cbm_cfg_size2, patch); | ||
218 | |||
219 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
220 | gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + | ||
221 | proj_ppc_in_gpc_stride_v() * ppc_index, | ||
222 | alpha_offset_in_chunk, patch); | ||
223 | |||
224 | alpha_offset_in_chunk += gr->alpha_cb_size * | ||
225 | gr->pes_tpc_count[ppc_index][gpc_index]; | ||
226 | |||
227 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
228 | gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + gpc_index), | ||
229 | gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size1) | | ||
230 | gr_gpcs_swdx_tc_beta_cb_size_div3_f(cbm_cfg_size1/3), | ||
231 | patch); | ||
232 | } | ||
233 | } | ||
234 | |||
235 | if (patch) | ||
236 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
237 | |||
238 | return 0; | ||
239 | } | ||
240 | |||
241 | static void gr_gm20b_commit_global_pagepool(struct gk20a *g, | ||
242 | struct channel_ctx_gk20a *ch_ctx, | ||
243 | u64 addr, u32 size, bool patch) | ||
244 | { | ||
245 | gr_gk20a_commit_global_pagepool(g, ch_ctx, addr, size, patch); | ||
246 | |||
247 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_rm_pagepool_r(), | ||
248 | gr_gpcs_swdx_rm_pagepool_total_pages_f(size) | | ||
249 | gr_gpcs_swdx_rm_pagepool_valid_true_f(), patch); | ||
250 | |||
251 | } | ||
252 | |||
253 | static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, | ||
254 | u32 class_num, u32 offset, u32 data) | ||
255 | { | ||
256 | gk20a_dbg_fn(""); | ||
257 | |||
258 | if (class_num == MAXWELL_COMPUTE_B) { | ||
259 | switch (offset << 2) { | ||
260 | case NVB1C0_SET_SHADER_EXCEPTIONS: | ||
261 | gk20a_gr_set_shader_exceptions(g, data); | ||
262 | break; | ||
263 | default: | ||
264 | goto fail; | ||
265 | } | ||
266 | } | ||
267 | |||
268 | if (class_num == MAXWELL_B) { | ||
269 | switch (offset << 2) { | ||
270 | case NVB197_SET_SHADER_EXCEPTIONS: | ||
271 | gk20a_gr_set_shader_exceptions(g, data); | ||
272 | break; | ||
273 | case NVB197_SET_CIRCULAR_BUFFER_SIZE: | ||
274 | g->ops.gr.set_circular_buffer_size(g, data); | ||
275 | break; | ||
276 | case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE: | ||
277 | g->ops.gr.set_alpha_circular_buffer_size(g, data); | ||
278 | break; | ||
279 | default: | ||
280 | goto fail; | ||
281 | } | ||
282 | } | ||
283 | return 0; | ||
284 | |||
285 | fail: | ||
286 | return -EINVAL; | ||
287 | } | ||
288 | |||
289 | static void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) | ||
290 | { | ||
291 | struct gr_gk20a *gr = &g->gr; | ||
292 | u32 gpc_index, ppc_index, stride, val; | ||
293 | u32 pd_ab_max_output; | ||
294 | u32 alpha_cb_size = data * 4; | ||
295 | |||
296 | gk20a_dbg_fn(""); | ||
297 | /* if (NO_ALPHA_BETA_TIMESLICE_SUPPORT_DEF) | ||
298 | return; */ | ||
299 | |||
300 | if (alpha_cb_size > gr->alpha_cb_size) | ||
301 | alpha_cb_size = gr->alpha_cb_size; | ||
302 | |||
303 | gk20a_writel(g, gr_ds_tga_constraintlogic_r(), | ||
304 | (gk20a_readl(g, gr_ds_tga_constraintlogic_r()) & | ||
305 | ~gr_ds_tga_constraintlogic_alpha_cbsize_f(~0)) | | ||
306 | gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size)); | ||
307 | |||
308 | pd_ab_max_output = alpha_cb_size * | ||
309 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() / | ||
310 | gr_pd_ab_dist_cfg1_max_output_granularity_v(); | ||
311 | |||
312 | gk20a_writel(g, gr_pd_ab_dist_cfg1_r(), | ||
313 | gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output)); | ||
314 | |||
315 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
316 | stride = proj_gpc_stride_v() * gpc_index; | ||
317 | |||
318 | for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; | ||
319 | ppc_index++) { | ||
320 | |||
321 | val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + | ||
322 | stride + | ||
323 | proj_ppc_in_gpc_stride_v() * ppc_index); | ||
324 | |||
325 | val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(), | ||
326 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size * | ||
327 | gr->pes_tpc_count[ppc_index][gpc_index])); | ||
328 | |||
329 | gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + | ||
330 | stride + | ||
331 | proj_ppc_in_gpc_stride_v() * ppc_index, val); | ||
332 | } | ||
333 | } | ||
334 | } | ||
335 | |||
336 | void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data) | ||
337 | { | ||
338 | struct gr_gk20a *gr = &g->gr; | ||
339 | u32 gpc_index, ppc_index, stride, val; | ||
340 | u32 cb_size = data * 4; | ||
341 | |||
342 | gk20a_dbg_fn(""); | ||
343 | |||
344 | if (cb_size > gr->attrib_cb_size) | ||
345 | cb_size = gr->attrib_cb_size; | ||
346 | |||
347 | gk20a_writel(g, gr_ds_tga_constraintlogic_r(), | ||
348 | (gk20a_readl(g, gr_ds_tga_constraintlogic_r()) & | ||
349 | ~gr_ds_tga_constraintlogic_beta_cbsize_f(~0)) | | ||
350 | gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size)); | ||
351 | |||
352 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
353 | stride = proj_gpc_stride_v() * gpc_index; | ||
354 | |||
355 | for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; | ||
356 | ppc_index++) { | ||
357 | |||
358 | val = gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + | ||
359 | stride + | ||
360 | proj_ppc_in_gpc_stride_v() * ppc_index); | ||
361 | |||
362 | val = set_field(val, | ||
363 | gr_gpc0_ppc0_cbm_beta_cb_size_v_m(), | ||
364 | gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size * | ||
365 | gr->pes_tpc_count[ppc_index][gpc_index])); | ||
366 | |||
367 | gk20a_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + | ||
368 | stride + | ||
369 | proj_ppc_in_gpc_stride_v() * ppc_index, val); | ||
370 | |||
371 | val = gk20a_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r( | ||
372 | ppc_index + gpc_index)); | ||
373 | |||
374 | val = set_field(val, | ||
375 | gr_gpcs_swdx_tc_beta_cb_size_v_m(), | ||
376 | gr_gpcs_swdx_tc_beta_cb_size_v_f(cb_size * | ||
377 | gr->gpc_ppc_count[gpc_index])); | ||
378 | val = set_field(val, | ||
379 | gr_gpcs_swdx_tc_beta_cb_size_div3_m(), | ||
380 | gr_gpcs_swdx_tc_beta_cb_size_div3_f((cb_size * | ||
381 | gr->gpc_ppc_count[gpc_index])/3)); | ||
382 | |||
383 | gk20a_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r( | ||
384 | ppc_index + gpc_index), val); | ||
385 | } | ||
386 | } | ||
387 | } | ||
388 | |||
389 | static void gr_gm20b_enable_hww_exceptions(struct gk20a *g) | ||
390 | { | ||
391 | gr_gk20a_enable_hww_exceptions(g); | ||
392 | |||
393 | gk20a_writel(g, gr_ds_hww_esr_2_r(), | ||
394 | gr_ds_hww_esr_2_en_enabled_f() | | ||
395 | gr_ds_hww_esr_2_reset_task_f()); | ||
396 | gk20a_writel(g, gr_ds_hww_report_mask_2_r(), | ||
397 | gr_ds_hww_report_mask_2_sph24_err_report_f()); | ||
398 | } | ||
399 | |||
400 | static void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) | ||
401 | { | ||
402 | /* setup sm warp esr report masks */ | ||
403 | gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(), | ||
404 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f() | | ||
405 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f() | | ||
406 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f() | | ||
407 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f() | | ||
408 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f() | | ||
409 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f() | | ||
410 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f() | | ||
411 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f() | | ||
412 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f() | | ||
413 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f() | | ||
414 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f() | | ||
415 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f() | | ||
416 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f() | | ||
417 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f() | | ||
418 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f() | | ||
419 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f() | | ||
420 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f() | | ||
421 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f() | | ||
422 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f() | | ||
423 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f() | | ||
424 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f() | | ||
425 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f()); | ||
426 | |||
427 | /* setup sm global esr report mask */ | ||
428 | gk20a_writel(g, gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(), | ||
429 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f() | | ||
430 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()); | ||
431 | } | ||
432 | |||
433 | static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) | ||
434 | { | ||
435 | bool valid = false; | ||
436 | |||
437 | switch (class_num) { | ||
438 | case MAXWELL_COMPUTE_B: | ||
439 | case MAXWELL_B: | ||
440 | case FERMI_TWOD_A: | ||
441 | case KEPLER_DMA_COPY_A: | ||
442 | case MAXWELL_DMA_COPY_A: | ||
443 | valid = true; | ||
444 | break; | ||
445 | |||
446 | default: | ||
447 | break; | ||
448 | } | ||
449 | |||
450 | return valid; | ||
451 | } | ||
452 | |||
453 | static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, | ||
454 | u32 *num_sm_dsm_perf_regs, | ||
455 | u32 **sm_dsm_perf_regs, | ||
456 | u32 *perf_register_stride) | ||
457 | { | ||
458 | gr_gk20a_get_sm_dsm_perf_regs(g, num_sm_dsm_perf_regs, | ||
459 | sm_dsm_perf_regs, | ||
460 | perf_register_stride); | ||
461 | *perf_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); | ||
462 | } | ||
463 | |||
464 | static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | ||
465 | u32 *num_sm_dsm_perf_regs, | ||
466 | u32 **sm_dsm_perf_regs, | ||
467 | u32 *ctrl_register_stride) | ||
468 | { | ||
469 | gr_gk20a_get_sm_dsm_perf_ctrl_regs(g, num_sm_dsm_perf_regs, | ||
470 | sm_dsm_perf_regs, | ||
471 | ctrl_register_stride); | ||
472 | *ctrl_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); | ||
473 | } | ||
474 | |||
475 | static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g) | ||
476 | { | ||
477 | struct gr_gk20a *gr = &g->gr; | ||
478 | u32 tpc_index, gpc_index; | ||
479 | u32 tpc_offset, gpc_offset; | ||
480 | u32 sm_id = 0, gpc_id = 0; | ||
481 | u32 sm_id_to_gpc_id[proj_scal_max_gpcs_v() * proj_scal_max_tpc_per_gpc_v()]; | ||
482 | u32 tpc_per_gpc; | ||
483 | |||
484 | gk20a_dbg_fn(""); | ||
485 | |||
486 | for (tpc_index = 0; tpc_index < gr->max_tpc_per_gpc_count; tpc_index++) { | ||
487 | for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { | ||
488 | gpc_offset = proj_gpc_stride_v() * gpc_index; | ||
489 | if (tpc_index < gr->gpc_tpc_count[gpc_index]) { | ||
490 | tpc_offset = proj_tpc_in_gpc_stride_v() * tpc_index; | ||
491 | |||
492 | gk20a_writel(g, gr_gpc0_tpc0_sm_cfg_r() + gpc_offset + tpc_offset, | ||
493 | gr_gpc0_tpc0_sm_cfg_sm_id_f(sm_id)); | ||
494 | gk20a_writel(g, gr_gpc0_gpm_pd_sm_id_r(tpc_index) + gpc_offset, | ||
495 | gr_gpc0_gpm_pd_sm_id_id_f(sm_id)); | ||
496 | gk20a_writel(g, gr_gpc0_tpc0_pe_cfg_smid_r() + gpc_offset + tpc_offset, | ||
497 | gr_gpc0_tpc0_pe_cfg_smid_value_f(sm_id)); | ||
498 | |||
499 | sm_id_to_gpc_id[sm_id] = gpc_index; | ||
500 | sm_id++; | ||
501 | } | ||
502 | } | ||
503 | } | ||
504 | |||
505 | for (tpc_index = 0, gpc_id = 0; | ||
506 | tpc_index < gr_pd_num_tpc_per_gpc__size_1_v(); | ||
507 | tpc_index++, gpc_id += 8) { | ||
508 | |||
509 | if (gpc_id >= gr->gpc_count) | ||
510 | gpc_id = 0; | ||
511 | |||
512 | tpc_per_gpc = | ||
513 | gr_pd_num_tpc_per_gpc_count0_f(gr->gpc_tpc_count[gpc_id + 0]) | | ||
514 | gr_pd_num_tpc_per_gpc_count1_f(gr->gpc_tpc_count[gpc_id + 1]) | | ||
515 | gr_pd_num_tpc_per_gpc_count2_f(gr->gpc_tpc_count[gpc_id + 2]) | | ||
516 | gr_pd_num_tpc_per_gpc_count3_f(gr->gpc_tpc_count[gpc_id + 3]) | | ||
517 | gr_pd_num_tpc_per_gpc_count4_f(gr->gpc_tpc_count[gpc_id + 4]) | | ||
518 | gr_pd_num_tpc_per_gpc_count5_f(gr->gpc_tpc_count[gpc_id + 5]) | | ||
519 | gr_pd_num_tpc_per_gpc_count6_f(gr->gpc_tpc_count[gpc_id + 6]) | | ||
520 | gr_pd_num_tpc_per_gpc_count7_f(gr->gpc_tpc_count[gpc_id + 7]); | ||
521 | |||
522 | gk20a_writel(g, gr_pd_num_tpc_per_gpc_r(tpc_index), tpc_per_gpc); | ||
523 | gk20a_writel(g, gr_ds_num_tpc_per_gpc_r(tpc_index), tpc_per_gpc); | ||
524 | } | ||
525 | |||
526 | /* gr__setup_pd_mapping stubbed for gk20a */ | ||
527 | gr_gk20a_setup_rop_mapping(g, gr); | ||
528 | |||
529 | for (gpc_index = 0; | ||
530 | gpc_index < gr_pd_dist_skip_table__size_1_v() * 4; | ||
531 | gpc_index += 4) { | ||
532 | |||
533 | gk20a_writel(g, gr_pd_dist_skip_table_r(gpc_index/4), | ||
534 | gr_pd_dist_skip_table_gpc_4n0_mask_f(gr->gpc_skip_mask[gpc_index]) || | ||
535 | gr_pd_dist_skip_table_gpc_4n1_mask_f(gr->gpc_skip_mask[gpc_index + 1]) || | ||
536 | gr_pd_dist_skip_table_gpc_4n2_mask_f(gr->gpc_skip_mask[gpc_index + 2]) || | ||
537 | gr_pd_dist_skip_table_gpc_4n3_mask_f(gr->gpc_skip_mask[gpc_index + 3])); | ||
538 | } | ||
539 | |||
540 | gk20a_writel(g, gr_cwd_fs_r(), | ||
541 | gr_cwd_fs_num_gpcs_f(gr->gpc_count) | | ||
542 | gr_cwd_fs_num_tpcs_f(gr->tpc_count)); | ||
543 | |||
544 | gk20a_writel(g, gr_bes_zrop_settings_r(), | ||
545 | gr_bes_zrop_settings_num_active_ltcs_f(gr->num_fbps)); | ||
546 | gk20a_writel(g, gr_bes_crop_settings_r(), | ||
547 | gr_bes_crop_settings_num_active_ltcs_f(gr->num_fbps)); | ||
548 | |||
549 | gk20a_writel(g, gr_bes_crop_debug3_r(), | ||
550 | gk20a_readl(g, gr_be0_crop_debug3_r()) | | ||
551 | gr_bes_crop_debug3_comp_vdc_4to2_disable_m()); | ||
552 | |||
553 | if (tegra_platform_is_silicon()) { | ||
554 | gk20a_writel(g, gr_fe_tpc_fs_r(), gr->pes_tpc_mask[0][0]); | ||
555 | |||
556 | gk20a_writel(g, gr_cwd_gpc_tpc_id_r(0), gr_cwd_gpc_tpc_id_tpc0_f(0) | | ||
557 | gr_cwd_gpc_tpc_id_tpc1_f(1)); | ||
558 | |||
559 | gk20a_writel(g, gr_cwd_sm_id_r(0), gr_cwd_sm_id_tpc0_f(0) | | ||
560 | gr_cwd_sm_id_tpc1_f(1)); | ||
561 | } else { | ||
562 | gk20a_writel(g, gr_fe_tpc_fs_r(), 1); | ||
563 | |||
564 | gk20a_writel(g, gr_cwd_gpc_tpc_id_r(0), gr_cwd_gpc_tpc_id_tpc0_f(0)); | ||
565 | |||
566 | gk20a_writel(g, gr_cwd_sm_id_r(0), gr_cwd_sm_id_tpc0_f(0)); | ||
567 | |||
568 | } | ||
569 | |||
570 | return 0; | ||
571 | } | ||
572 | |||
573 | void gm20b_init_gr(struct gpu_ops *gops) | ||
574 | { | ||
575 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | ||
576 | gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; | ||
577 | gops->gr.cb_size_default = gr_gm20b_cb_size_default; | ||
578 | gops->gr.calc_global_ctx_buffer_size = | ||
579 | gr_gm20b_calc_global_ctx_buffer_size; | ||
580 | gops->gr.commit_global_attrib_cb = gr_gk20a_commit_global_attrib_cb; | ||
581 | gops->gr.commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb; | ||
582 | gops->gr.commit_global_cb_manager = gr_gm20b_commit_global_cb_manager; | ||
583 | gops->gr.commit_global_pagepool = gr_gm20b_commit_global_pagepool; | ||
584 | gops->gr.handle_sw_method = gr_gm20b_handle_sw_method; | ||
585 | gops->gr.set_alpha_circular_buffer_size = gr_gm20b_set_alpha_circular_buffer_size; | ||
586 | gops->gr.set_circular_buffer_size = gr_gm20b_set_circular_buffer_size; | ||
587 | gops->gr.enable_hww_exceptions = gr_gm20b_enable_hww_exceptions; | ||
588 | gops->gr.is_valid_class = gr_gm20b_is_valid_class; | ||
589 | gops->gr.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs; | ||
590 | gops->gr.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs; | ||
591 | gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep; | ||
592 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; | ||
593 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h new file mode 100644 index 00000000..8348b9d9 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * GM20B GPC MMU | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVHOST_GM20B_GR_MMU_H | ||
17 | #define _NVHOST_GM20B_GR_MMU_H | ||
18 | struct gk20a; | ||
19 | |||
20 | enum { | ||
21 | MAXWELL_B = 0xB197, | ||
22 | MAXWELL_COMPUTE_B = 0xB1C0, | ||
23 | MAXWELL_DMA_COPY_A = 0xB0B5, | ||
24 | }; | ||
25 | |||
26 | #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc | ||
27 | #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 | ||
28 | #define NVB197_SET_SHADER_EXCEPTIONS 0x1528 | ||
29 | #define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 | ||
30 | |||
31 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | ||
32 | void gm20b_init_gr(struct gpu_ops *gops); | ||
33 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c new file mode 100644 index 00000000..286e5fa5 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -0,0 +1,51 @@ | |||
1 | /* | ||
2 | * GM20B Graphics | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | #include "gk20a/gk20a.h" | ||
19 | |||
20 | #include "ltc_gm20b.h" | ||
21 | #include "gr_gm20b.h" | ||
22 | #include "ltc_gm20b.h" | ||
23 | #include "fb_gm20b.h" | ||
24 | #include "gm20b_gating_reglist.h" | ||
25 | |||
26 | struct gpu_ops gm20b_ops = { | ||
27 | .clock_gating = { | ||
28 | .slcg_gr_load_gating_prod = | ||
29 | gr_gm20b_slcg_gr_load_gating_prod, | ||
30 | .slcg_perf_load_gating_prod = | ||
31 | gr_gm20b_slcg_perf_load_gating_prod, | ||
32 | .blcg_gr_load_gating_prod = | ||
33 | gr_gm20b_blcg_gr_load_gating_prod, | ||
34 | .pg_gr_load_gating_prod = | ||
35 | gr_gm20b_pg_gr_load_gating_prod, | ||
36 | .slcg_therm_load_gating_prod = | ||
37 | gr_gm20b_slcg_therm_load_gating_prod, | ||
38 | } | ||
39 | }; | ||
40 | |||
41 | int gm20b_init_hal(struct gpu_ops *gops) | ||
42 | { | ||
43 | *gops = gm20b_ops; | ||
44 | gm20b_init_ltc(gops); | ||
45 | gm20b_init_gr(gops); | ||
46 | gm20b_init_ltc(gops); | ||
47 | gm20b_init_fb(gops); | ||
48 | gops->name = "gm20b"; | ||
49 | |||
50 | return 0; | ||
51 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h new file mode 100644 index 00000000..99e193fc --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * GM20B Graphics | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVHOST_HAL_GM20B_H | ||
17 | #define _NVHOST_HAL_GM20B_H | ||
18 | struct gpu_ops; | ||
19 | |||
20 | int gm20b_init_hal(struct gpu_ops *gops); | ||
21 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_bus_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_bus_gm20b.h new file mode 100644 index 00000000..800165fc --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_bus_gm20b.h | |||
@@ -0,0 +1,105 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_bus_gm20b_h_ | ||
51 | #define _hw_bus_gm20b_h_ | ||
52 | |||
53 | static inline u32 bus_bar1_block_r(void) | ||
54 | { | ||
55 | return 0x00001704; | ||
56 | } | ||
57 | static inline u32 bus_bar1_block_ptr_f(u32 v) | ||
58 | { | ||
59 | return (v & 0xfffffff) << 0; | ||
60 | } | ||
61 | static inline u32 bus_bar1_block_target_vid_mem_f(void) | ||
62 | { | ||
63 | return 0x0; | ||
64 | } | ||
65 | static inline u32 bus_bar1_block_mode_virtual_f(void) | ||
66 | { | ||
67 | return 0x80000000; | ||
68 | } | ||
69 | static inline u32 bus_bar1_block_ptr_shift_v(void) | ||
70 | { | ||
71 | return 0x0000000c; | ||
72 | } | ||
73 | static inline u32 bus_intr_0_r(void) | ||
74 | { | ||
75 | return 0x00001100; | ||
76 | } | ||
77 | static inline u32 bus_intr_0_pri_squash_m(void) | ||
78 | { | ||
79 | return 0x1 << 1; | ||
80 | } | ||
81 | static inline u32 bus_intr_0_pri_fecserr_m(void) | ||
82 | { | ||
83 | return 0x1 << 2; | ||
84 | } | ||
85 | static inline u32 bus_intr_0_pri_timeout_m(void) | ||
86 | { | ||
87 | return 0x1 << 3; | ||
88 | } | ||
89 | static inline u32 bus_intr_en_0_r(void) | ||
90 | { | ||
91 | return 0x00001140; | ||
92 | } | ||
93 | static inline u32 bus_intr_en_0_pri_squash_m(void) | ||
94 | { | ||
95 | return 0x1 << 1; | ||
96 | } | ||
97 | static inline u32 bus_intr_en_0_pri_fecserr_m(void) | ||
98 | { | ||
99 | return 0x1 << 2; | ||
100 | } | ||
101 | static inline u32 bus_intr_en_0_pri_timeout_m(void) | ||
102 | { | ||
103 | return 0x1 << 3; | ||
104 | } | ||
105 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ccsr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ccsr_gm20b.h new file mode 100644 index 00000000..9dd03ee1 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_ccsr_gm20b.h | |||
@@ -0,0 +1,109 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ccsr_gm20b_h_ | ||
51 | #define _hw_ccsr_gm20b_h_ | ||
52 | |||
53 | static inline u32 ccsr_channel_inst_r(u32 i) | ||
54 | { | ||
55 | return 0x00800000 + i*8; | ||
56 | } | ||
57 | static inline u32 ccsr_channel_inst__size_1_v(void) | ||
58 | { | ||
59 | return 0x00000200; | ||
60 | } | ||
61 | static inline u32 ccsr_channel_inst_ptr_f(u32 v) | ||
62 | { | ||
63 | return (v & 0xfffffff) << 0; | ||
64 | } | ||
65 | static inline u32 ccsr_channel_inst_target_vid_mem_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 ccsr_channel_inst_bind_false_f(void) | ||
70 | { | ||
71 | return 0x0; | ||
72 | } | ||
73 | static inline u32 ccsr_channel_inst_bind_true_f(void) | ||
74 | { | ||
75 | return 0x80000000; | ||
76 | } | ||
77 | static inline u32 ccsr_channel_r(u32 i) | ||
78 | { | ||
79 | return 0x00800004 + i*8; | ||
80 | } | ||
81 | static inline u32 ccsr_channel__size_1_v(void) | ||
82 | { | ||
83 | return 0x00000200; | ||
84 | } | ||
85 | static inline u32 ccsr_channel_enable_v(u32 r) | ||
86 | { | ||
87 | return (r >> 0) & 0x1; | ||
88 | } | ||
89 | static inline u32 ccsr_channel_enable_set_f(u32 v) | ||
90 | { | ||
91 | return (v & 0x1) << 10; | ||
92 | } | ||
93 | static inline u32 ccsr_channel_enable_set_true_f(void) | ||
94 | { | ||
95 | return 0x400; | ||
96 | } | ||
97 | static inline u32 ccsr_channel_enable_clr_true_f(void) | ||
98 | { | ||
99 | return 0x800; | ||
100 | } | ||
101 | static inline u32 ccsr_channel_status_v(u32 r) | ||
102 | { | ||
103 | return (r >> 24) & 0xf; | ||
104 | } | ||
105 | static inline u32 ccsr_channel_busy_v(u32 r) | ||
106 | { | ||
107 | return (r >> 28) & 0x1; | ||
108 | } | ||
109 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_chiplet_pwr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_chiplet_pwr_gm20b.h new file mode 100644 index 00000000..a9e28cb5 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_chiplet_pwr_gm20b.h | |||
@@ -0,0 +1,85 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_chiplet_pwr_gm20b_h_ | ||
51 | #define _hw_chiplet_pwr_gm20b_h_ | ||
52 | |||
53 | static inline u32 chiplet_pwr_gpcs_weight_6_r(void) | ||
54 | { | ||
55 | return 0x0010e018; | ||
56 | } | ||
57 | static inline u32 chiplet_pwr_gpcs_weight_7_r(void) | ||
58 | { | ||
59 | return 0x0010e01c; | ||
60 | } | ||
61 | static inline u32 chiplet_pwr_gpcs_config_1_r(void) | ||
62 | { | ||
63 | return 0x0010e03c; | ||
64 | } | ||
65 | static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void) | ||
66 | { | ||
67 | return 0x1; | ||
68 | } | ||
69 | static inline u32 chiplet_pwr_fbps_weight_0_r(void) | ||
70 | { | ||
71 | return 0x0010e100; | ||
72 | } | ||
73 | static inline u32 chiplet_pwr_fbps_weight_1_r(void) | ||
74 | { | ||
75 | return 0x0010e104; | ||
76 | } | ||
77 | static inline u32 chiplet_pwr_fbps_config_1_r(void) | ||
78 | { | ||
79 | return 0x0010e13c; | ||
80 | } | ||
81 | static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void) | ||
82 | { | ||
83 | return 0x1; | ||
84 | } | ||
85 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h new file mode 100644 index 00000000..01161f17 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | |||
@@ -0,0 +1,181 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ctxsw_prog_gm20b_h_ | ||
51 | #define _hw_ctxsw_prog_gm20b_h_ | ||
52 | |||
53 | static inline u32 ctxsw_prog_fecs_header_v(void) | ||
54 | { | ||
55 | return 0x00000100; | ||
56 | } | ||
57 | static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) | ||
58 | { | ||
59 | return 0x00000008; | ||
60 | } | ||
61 | static inline u32 ctxsw_prog_main_image_patch_count_o(void) | ||
62 | { | ||
63 | return 0x00000010; | ||
64 | } | ||
65 | static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) | ||
66 | { | ||
67 | return 0x00000014; | ||
68 | } | ||
69 | static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) | ||
70 | { | ||
71 | return 0x00000018; | ||
72 | } | ||
73 | static inline u32 ctxsw_prog_main_image_zcull_o(void) | ||
74 | { | ||
75 | return 0x0000001c; | ||
76 | } | ||
77 | static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) | ||
78 | { | ||
79 | return 0x00000001; | ||
80 | } | ||
81 | static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) | ||
82 | { | ||
83 | return 0x00000002; | ||
84 | } | ||
85 | static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) | ||
86 | { | ||
87 | return 0x00000020; | ||
88 | } | ||
89 | static inline u32 ctxsw_prog_main_image_pm_o(void) | ||
90 | { | ||
91 | return 0x00000028; | ||
92 | } | ||
93 | static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r) | ||
94 | { | ||
95 | return (r >> 0) & 0x7; | ||
96 | } | ||
97 | static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_v(void) | ||
98 | { | ||
99 | return 0x00000000; | ||
100 | } | ||
101 | static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) | ||
102 | { | ||
103 | return 0x0000002c; | ||
104 | } | ||
105 | static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) | ||
106 | { | ||
107 | return 0x000000f4; | ||
108 | } | ||
109 | static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) | ||
110 | { | ||
111 | return 0x000000f8; | ||
112 | } | ||
113 | static inline u32 ctxsw_prog_main_image_magic_value_o(void) | ||
114 | { | ||
115 | return 0x000000fc; | ||
116 | } | ||
117 | static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) | ||
118 | { | ||
119 | return 0x600dc0de; | ||
120 | } | ||
121 | static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) | ||
122 | { | ||
123 | return 0x0000000c; | ||
124 | } | ||
125 | static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) | ||
126 | { | ||
127 | return (r >> 0) & 0xffff; | ||
128 | } | ||
129 | static inline u32 ctxsw_prog_local_image_ppc_info_o(void) | ||
130 | { | ||
131 | return 0x000000f4; | ||
132 | } | ||
133 | static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) | ||
134 | { | ||
135 | return (r >> 0) & 0xffff; | ||
136 | } | ||
137 | static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) | ||
138 | { | ||
139 | return (r >> 16) & 0xffff; | ||
140 | } | ||
141 | static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) | ||
142 | { | ||
143 | return 0x000000f8; | ||
144 | } | ||
145 | static inline u32 ctxsw_prog_local_magic_value_o(void) | ||
146 | { | ||
147 | return 0x000000fc; | ||
148 | } | ||
149 | static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) | ||
150 | { | ||
151 | return 0xad0becab; | ||
152 | } | ||
153 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) | ||
154 | { | ||
155 | return 0x000000ec; | ||
156 | } | ||
157 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) | ||
158 | { | ||
159 | return (r >> 0) & 0xffff; | ||
160 | } | ||
161 | static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) | ||
162 | { | ||
163 | return (r >> 16) & 0xff; | ||
164 | } | ||
165 | static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) | ||
166 | { | ||
167 | return 0x00000100; | ||
168 | } | ||
169 | static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) | ||
170 | { | ||
171 | return 0x00000004; | ||
172 | } | ||
173 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) | ||
174 | { | ||
175 | return 0x00000000; | ||
176 | } | ||
177 | static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) | ||
178 | { | ||
179 | return 0x00000002; | ||
180 | } | ||
181 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h new file mode 100644 index 00000000..f3ad6f26 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h | |||
@@ -0,0 +1,201 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_fb_gm20b_h_ | ||
51 | #define _hw_fb_gm20b_h_ | ||
52 | |||
53 | static inline u32 fb_fbhub_num_active_ltcs_r(void) | ||
54 | { | ||
55 | return 0x00100800; | ||
56 | } | ||
57 | static inline u32 fb_mmu_ctrl_r(void) | ||
58 | { | ||
59 | return 0x00100c80; | ||
60 | } | ||
61 | static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) | ||
62 | { | ||
63 | return (v & 0x1) << 0; | ||
64 | } | ||
65 | static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) | ||
70 | { | ||
71 | return (r >> 15) & 0x1; | ||
72 | } | ||
73 | static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) | ||
74 | { | ||
75 | return 0x0; | ||
76 | } | ||
77 | static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) | ||
78 | { | ||
79 | return (r >> 16) & 0xff; | ||
80 | } | ||
81 | static inline u32 fb_mmu_invalidate_pdb_r(void) | ||
82 | { | ||
83 | return 0x00100cb8; | ||
84 | } | ||
85 | static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) | ||
86 | { | ||
87 | return 0x0; | ||
88 | } | ||
89 | static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) | ||
90 | { | ||
91 | return (v & 0xfffffff) << 4; | ||
92 | } | ||
93 | static inline u32 fb_mmu_invalidate_r(void) | ||
94 | { | ||
95 | return 0x00100cbc; | ||
96 | } | ||
97 | static inline u32 fb_mmu_invalidate_all_va_true_f(void) | ||
98 | { | ||
99 | return 0x1; | ||
100 | } | ||
101 | static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) | ||
102 | { | ||
103 | return 0x2; | ||
104 | } | ||
105 | static inline u32 fb_mmu_invalidate_trigger_s(void) | ||
106 | { | ||
107 | return 1; | ||
108 | } | ||
109 | static inline u32 fb_mmu_invalidate_trigger_f(u32 v) | ||
110 | { | ||
111 | return (v & 0x1) << 31; | ||
112 | } | ||
113 | static inline u32 fb_mmu_invalidate_trigger_m(void) | ||
114 | { | ||
115 | return 0x1 << 31; | ||
116 | } | ||
117 | static inline u32 fb_mmu_invalidate_trigger_v(u32 r) | ||
118 | { | ||
119 | return (r >> 31) & 0x1; | ||
120 | } | ||
121 | static inline u32 fb_mmu_invalidate_trigger_true_f(void) | ||
122 | { | ||
123 | return 0x80000000; | ||
124 | } | ||
125 | static inline u32 fb_mmu_debug_wr_r(void) | ||
126 | { | ||
127 | return 0x00100cc8; | ||
128 | } | ||
129 | static inline u32 fb_mmu_debug_wr_aperture_s(void) | ||
130 | { | ||
131 | return 2; | ||
132 | } | ||
133 | static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) | ||
134 | { | ||
135 | return (v & 0x3) << 0; | ||
136 | } | ||
137 | static inline u32 fb_mmu_debug_wr_aperture_m(void) | ||
138 | { | ||
139 | return 0x3 << 0; | ||
140 | } | ||
141 | static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) | ||
142 | { | ||
143 | return (r >> 0) & 0x3; | ||
144 | } | ||
145 | static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) | ||
146 | { | ||
147 | return 0x0; | ||
148 | } | ||
149 | static inline u32 fb_mmu_debug_wr_vol_false_f(void) | ||
150 | { | ||
151 | return 0x0; | ||
152 | } | ||
153 | static inline u32 fb_mmu_debug_wr_vol_true_v(void) | ||
154 | { | ||
155 | return 0x00000001; | ||
156 | } | ||
157 | static inline u32 fb_mmu_debug_wr_vol_true_f(void) | ||
158 | { | ||
159 | return 0x4; | ||
160 | } | ||
161 | static inline u32 fb_mmu_debug_wr_addr_v(u32 r) | ||
162 | { | ||
163 | return (r >> 4) & 0xfffffff; | ||
164 | } | ||
165 | static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) | ||
166 | { | ||
167 | return 0x0000000c; | ||
168 | } | ||
169 | static inline u32 fb_mmu_debug_rd_r(void) | ||
170 | { | ||
171 | return 0x00100ccc; | ||
172 | } | ||
173 | static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) | ||
174 | { | ||
175 | return 0x0; | ||
176 | } | ||
177 | static inline u32 fb_mmu_debug_rd_vol_false_f(void) | ||
178 | { | ||
179 | return 0x0; | ||
180 | } | ||
181 | static inline u32 fb_mmu_debug_rd_addr_v(u32 r) | ||
182 | { | ||
183 | return (r >> 4) & 0xfffffff; | ||
184 | } | ||
185 | static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) | ||
186 | { | ||
187 | return 0x0000000c; | ||
188 | } | ||
189 | static inline u32 fb_mmu_debug_ctrl_r(void) | ||
190 | { | ||
191 | return 0x00100cc4; | ||
192 | } | ||
193 | static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) | ||
194 | { | ||
195 | return (r >> 16) & 0x1; | ||
196 | } | ||
197 | static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) | ||
198 | { | ||
199 | return 0x00000001; | ||
200 | } | ||
201 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h new file mode 100644 index 00000000..2b8bd9ce --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h | |||
@@ -0,0 +1,509 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_fifo_gm20b_h_ | ||
51 | #define _hw_fifo_gm20b_h_ | ||
52 | |||
53 | static inline u32 fifo_bar1_base_r(void) | ||
54 | { | ||
55 | return 0x00002254; | ||
56 | } | ||
57 | static inline u32 fifo_bar1_base_ptr_f(u32 v) | ||
58 | { | ||
59 | return (v & 0xfffffff) << 0; | ||
60 | } | ||
61 | static inline u32 fifo_bar1_base_ptr_align_shift_v(void) | ||
62 | { | ||
63 | return 0x0000000c; | ||
64 | } | ||
65 | static inline u32 fifo_bar1_base_valid_false_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 fifo_bar1_base_valid_true_f(void) | ||
70 | { | ||
71 | return 0x10000000; | ||
72 | } | ||
73 | static inline u32 fifo_runlist_base_r(void) | ||
74 | { | ||
75 | return 0x00002270; | ||
76 | } | ||
77 | static inline u32 fifo_runlist_base_ptr_f(u32 v) | ||
78 | { | ||
79 | return (v & 0xfffffff) << 0; | ||
80 | } | ||
81 | static inline u32 fifo_runlist_base_target_vid_mem_f(void) | ||
82 | { | ||
83 | return 0x0; | ||
84 | } | ||
85 | static inline u32 fifo_runlist_r(void) | ||
86 | { | ||
87 | return 0x00002274; | ||
88 | } | ||
89 | static inline u32 fifo_runlist_engine_f(u32 v) | ||
90 | { | ||
91 | return (v & 0xf) << 20; | ||
92 | } | ||
93 | static inline u32 fifo_eng_runlist_base_r(u32 i) | ||
94 | { | ||
95 | return 0x00002280 + i*8; | ||
96 | } | ||
97 | static inline u32 fifo_eng_runlist_base__size_1_v(void) | ||
98 | { | ||
99 | return 0x00000001; | ||
100 | } | ||
101 | static inline u32 fifo_eng_runlist_r(u32 i) | ||
102 | { | ||
103 | return 0x00002284 + i*8; | ||
104 | } | ||
105 | static inline u32 fifo_eng_runlist__size_1_v(void) | ||
106 | { | ||
107 | return 0x00000001; | ||
108 | } | ||
109 | static inline u32 fifo_eng_runlist_length_f(u32 v) | ||
110 | { | ||
111 | return (v & 0xffff) << 0; | ||
112 | } | ||
113 | static inline u32 fifo_eng_runlist_pending_true_f(void) | ||
114 | { | ||
115 | return 0x100000; | ||
116 | } | ||
117 | static inline u32 fifo_pb_timeslice_r(u32 i) | ||
118 | { | ||
119 | return 0x00002350 + i*4; | ||
120 | } | ||
121 | static inline u32 fifo_pb_timeslice_timeout_16_f(void) | ||
122 | { | ||
123 | return 0x10; | ||
124 | } | ||
125 | static inline u32 fifo_pb_timeslice_timescale_0_f(void) | ||
126 | { | ||
127 | return 0x0; | ||
128 | } | ||
129 | static inline u32 fifo_pb_timeslice_enable_true_f(void) | ||
130 | { | ||
131 | return 0x10000000; | ||
132 | } | ||
133 | static inline u32 fifo_pbdma_map_r(u32 i) | ||
134 | { | ||
135 | return 0x00002390 + i*4; | ||
136 | } | ||
137 | static inline u32 fifo_intr_0_r(void) | ||
138 | { | ||
139 | return 0x00002100; | ||
140 | } | ||
141 | static inline u32 fifo_intr_0_bind_error_pending_f(void) | ||
142 | { | ||
143 | return 0x1; | ||
144 | } | ||
145 | static inline u32 fifo_intr_0_bind_error_reset_f(void) | ||
146 | { | ||
147 | return 0x1; | ||
148 | } | ||
149 | static inline u32 fifo_intr_0_sched_error_pending_f(void) | ||
150 | { | ||
151 | return 0x100; | ||
152 | } | ||
153 | static inline u32 fifo_intr_0_sched_error_reset_f(void) | ||
154 | { | ||
155 | return 0x100; | ||
156 | } | ||
157 | static inline u32 fifo_intr_0_chsw_error_pending_f(void) | ||
158 | { | ||
159 | return 0x10000; | ||
160 | } | ||
161 | static inline u32 fifo_intr_0_chsw_error_reset_f(void) | ||
162 | { | ||
163 | return 0x10000; | ||
164 | } | ||
165 | static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) | ||
166 | { | ||
167 | return 0x800000; | ||
168 | } | ||
169 | static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) | ||
170 | { | ||
171 | return 0x800000; | ||
172 | } | ||
173 | static inline u32 fifo_intr_0_lb_error_pending_f(void) | ||
174 | { | ||
175 | return 0x1000000; | ||
176 | } | ||
177 | static inline u32 fifo_intr_0_lb_error_reset_f(void) | ||
178 | { | ||
179 | return 0x1000000; | ||
180 | } | ||
181 | static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) | ||
182 | { | ||
183 | return 0x8000000; | ||
184 | } | ||
185 | static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) | ||
186 | { | ||
187 | return 0x8000000; | ||
188 | } | ||
189 | static inline u32 fifo_intr_0_mmu_fault_pending_f(void) | ||
190 | { | ||
191 | return 0x10000000; | ||
192 | } | ||
193 | static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) | ||
194 | { | ||
195 | return 0x20000000; | ||
196 | } | ||
197 | static inline u32 fifo_intr_0_runlist_event_pending_f(void) | ||
198 | { | ||
199 | return 0x40000000; | ||
200 | } | ||
201 | static inline u32 fifo_intr_0_channel_intr_pending_f(void) | ||
202 | { | ||
203 | return 0x80000000; | ||
204 | } | ||
205 | static inline u32 fifo_intr_en_0_r(void) | ||
206 | { | ||
207 | return 0x00002140; | ||
208 | } | ||
209 | static inline u32 fifo_intr_en_1_r(void) | ||
210 | { | ||
211 | return 0x00002528; | ||
212 | } | ||
213 | static inline u32 fifo_intr_bind_error_r(void) | ||
214 | { | ||
215 | return 0x0000252c; | ||
216 | } | ||
217 | static inline u32 fifo_intr_sched_error_r(void) | ||
218 | { | ||
219 | return 0x0000254c; | ||
220 | } | ||
221 | static inline u32 fifo_intr_sched_error_code_f(u32 v) | ||
222 | { | ||
223 | return (v & 0xff) << 0; | ||
224 | } | ||
225 | static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) | ||
226 | { | ||
227 | return 0x0000000a; | ||
228 | } | ||
229 | static inline u32 fifo_intr_chsw_error_r(void) | ||
230 | { | ||
231 | return 0x0000256c; | ||
232 | } | ||
233 | static inline u32 fifo_intr_mmu_fault_id_r(void) | ||
234 | { | ||
235 | return 0x0000259c; | ||
236 | } | ||
237 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) | ||
238 | { | ||
239 | return 0x00000000; | ||
240 | } | ||
241 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) | ||
242 | { | ||
243 | return 0x0; | ||
244 | } | ||
245 | static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) | ||
246 | { | ||
247 | return 0x00002800 + i*16; | ||
248 | } | ||
249 | static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) | ||
250 | { | ||
251 | return (r >> 0) & 0xfffffff; | ||
252 | } | ||
253 | static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) | ||
254 | { | ||
255 | return 0x0000000c; | ||
256 | } | ||
257 | static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) | ||
258 | { | ||
259 | return 0x00002804 + i*16; | ||
260 | } | ||
261 | static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) | ||
262 | { | ||
263 | return 0x00002808 + i*16; | ||
264 | } | ||
265 | static inline u32 fifo_intr_mmu_fault_info_r(u32 i) | ||
266 | { | ||
267 | return 0x0000280c + i*16; | ||
268 | } | ||
269 | static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) | ||
270 | { | ||
271 | return (r >> 0) & 0xf; | ||
272 | } | ||
273 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) | ||
274 | { | ||
275 | return (r >> 6) & 0x1; | ||
276 | } | ||
277 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) | ||
278 | { | ||
279 | return 0x00000000; | ||
280 | } | ||
281 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) | ||
282 | { | ||
283 | return 0x00000001; | ||
284 | } | ||
285 | static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) | ||
286 | { | ||
287 | return (r >> 8) & 0x3f; | ||
288 | } | ||
289 | static inline u32 fifo_intr_pbdma_id_r(void) | ||
290 | { | ||
291 | return 0x000025a0; | ||
292 | } | ||
293 | static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) | ||
294 | { | ||
295 | return (v & 0x1) << (0 + i*1); | ||
296 | } | ||
297 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) | ||
298 | { | ||
299 | return 0x00000001; | ||
300 | } | ||
301 | static inline u32 fifo_intr_runlist_r(void) | ||
302 | { | ||
303 | return 0x00002a00; | ||
304 | } | ||
305 | static inline u32 fifo_fb_timeout_r(void) | ||
306 | { | ||
307 | return 0x00002a04; | ||
308 | } | ||
309 | static inline u32 fifo_fb_timeout_period_m(void) | ||
310 | { | ||
311 | return 0x3fffffff << 0; | ||
312 | } | ||
313 | static inline u32 fifo_fb_timeout_period_max_f(void) | ||
314 | { | ||
315 | return 0x3fffffff; | ||
316 | } | ||
317 | static inline u32 fifo_error_sched_disable_r(void) | ||
318 | { | ||
319 | return 0x0000262c; | ||
320 | } | ||
321 | static inline u32 fifo_sched_disable_r(void) | ||
322 | { | ||
323 | return 0x00002630; | ||
324 | } | ||
325 | static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) | ||
326 | { | ||
327 | return (v & 0x1) << (0 + i*1); | ||
328 | } | ||
329 | static inline u32 fifo_sched_disable_runlist_m(u32 i) | ||
330 | { | ||
331 | return 0x1 << (0 + i*1); | ||
332 | } | ||
333 | static inline u32 fifo_sched_disable_true_v(void) | ||
334 | { | ||
335 | return 0x00000001; | ||
336 | } | ||
337 | static inline u32 fifo_preempt_r(void) | ||
338 | { | ||
339 | return 0x00002634; | ||
340 | } | ||
341 | static inline u32 fifo_preempt_pending_true_f(void) | ||
342 | { | ||
343 | return 0x100000; | ||
344 | } | ||
345 | static inline u32 fifo_preempt_type_channel_f(void) | ||
346 | { | ||
347 | return 0x0; | ||
348 | } | ||
349 | static inline u32 fifo_preempt_chid_f(u32 v) | ||
350 | { | ||
351 | return (v & 0xfff) << 0; | ||
352 | } | ||
353 | static inline u32 fifo_trigger_mmu_fault_r(u32 i) | ||
354 | { | ||
355 | return 0x00002a30 + i*4; | ||
356 | } | ||
357 | static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) | ||
358 | { | ||
359 | return (v & 0x1f) << 0; | ||
360 | } | ||
361 | static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) | ||
362 | { | ||
363 | return (v & 0x1) << 8; | ||
364 | } | ||
365 | static inline u32 fifo_engine_status_r(u32 i) | ||
366 | { | ||
367 | return 0x00002640 + i*8; | ||
368 | } | ||
369 | static inline u32 fifo_engine_status__size_1_v(void) | ||
370 | { | ||
371 | return 0x00000002; | ||
372 | } | ||
373 | static inline u32 fifo_engine_status_id_v(u32 r) | ||
374 | { | ||
375 | return (r >> 0) & 0xfff; | ||
376 | } | ||
377 | static inline u32 fifo_engine_status_id_type_v(u32 r) | ||
378 | { | ||
379 | return (r >> 12) & 0x1; | ||
380 | } | ||
381 | static inline u32 fifo_engine_status_id_type_chid_v(void) | ||
382 | { | ||
383 | return 0x00000000; | ||
384 | } | ||
385 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) | ||
386 | { | ||
387 | return (r >> 13) & 0x7; | ||
388 | } | ||
389 | static inline u32 fifo_engine_status_ctx_status_valid_v(void) | ||
390 | { | ||
391 | return 0x00000001; | ||
392 | } | ||
393 | static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) | ||
394 | { | ||
395 | return 0x00000005; | ||
396 | } | ||
397 | static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) | ||
398 | { | ||
399 | return 0x00000006; | ||
400 | } | ||
401 | static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) | ||
402 | { | ||
403 | return 0x00000007; | ||
404 | } | ||
405 | static inline u32 fifo_engine_status_next_id_v(u32 r) | ||
406 | { | ||
407 | return (r >> 16) & 0xfff; | ||
408 | } | ||
409 | static inline u32 fifo_engine_status_next_id_type_v(u32 r) | ||
410 | { | ||
411 | return (r >> 28) & 0x1; | ||
412 | } | ||
413 | static inline u32 fifo_engine_status_next_id_type_chid_v(void) | ||
414 | { | ||
415 | return 0x00000000; | ||
416 | } | ||
417 | static inline u32 fifo_engine_status_faulted_v(u32 r) | ||
418 | { | ||
419 | return (r >> 30) & 0x1; | ||
420 | } | ||
421 | static inline u32 fifo_engine_status_faulted_true_v(void) | ||
422 | { | ||
423 | return 0x00000001; | ||
424 | } | ||
425 | static inline u32 fifo_engine_status_engine_v(u32 r) | ||
426 | { | ||
427 | return (r >> 31) & 0x1; | ||
428 | } | ||
429 | static inline u32 fifo_engine_status_engine_idle_v(void) | ||
430 | { | ||
431 | return 0x00000000; | ||
432 | } | ||
433 | static inline u32 fifo_engine_status_engine_busy_v(void) | ||
434 | { | ||
435 | return 0x00000001; | ||
436 | } | ||
437 | static inline u32 fifo_engine_status_ctxsw_v(u32 r) | ||
438 | { | ||
439 | return (r >> 15) & 0x1; | ||
440 | } | ||
441 | static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) | ||
442 | { | ||
443 | return 0x00000001; | ||
444 | } | ||
445 | static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) | ||
446 | { | ||
447 | return 0x8000; | ||
448 | } | ||
449 | static inline u32 fifo_pbdma_status_r(u32 i) | ||
450 | { | ||
451 | return 0x00003080 + i*4; | ||
452 | } | ||
453 | static inline u32 fifo_pbdma_status__size_1_v(void) | ||
454 | { | ||
455 | return 0x00000001; | ||
456 | } | ||
457 | static inline u32 fifo_pbdma_status_id_v(u32 r) | ||
458 | { | ||
459 | return (r >> 0) & 0xfff; | ||
460 | } | ||
461 | static inline u32 fifo_pbdma_status_id_type_v(u32 r) | ||
462 | { | ||
463 | return (r >> 12) & 0x1; | ||
464 | } | ||
465 | static inline u32 fifo_pbdma_status_id_type_chid_v(void) | ||
466 | { | ||
467 | return 0x00000000; | ||
468 | } | ||
469 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) | ||
470 | { | ||
471 | return (r >> 13) & 0x7; | ||
472 | } | ||
473 | static inline u32 fifo_pbdma_status_chan_status_valid_v(void) | ||
474 | { | ||
475 | return 0x00000001; | ||
476 | } | ||
477 | static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) | ||
478 | { | ||
479 | return 0x00000005; | ||
480 | } | ||
481 | static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) | ||
482 | { | ||
483 | return 0x00000006; | ||
484 | } | ||
485 | static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) | ||
486 | { | ||
487 | return 0x00000007; | ||
488 | } | ||
489 | static inline u32 fifo_pbdma_status_next_id_v(u32 r) | ||
490 | { | ||
491 | return (r >> 16) & 0xfff; | ||
492 | } | ||
493 | static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) | ||
494 | { | ||
495 | return (r >> 28) & 0x1; | ||
496 | } | ||
497 | static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) | ||
498 | { | ||
499 | return 0x00000000; | ||
500 | } | ||
501 | static inline u32 fifo_pbdma_status_chsw_v(u32 r) | ||
502 | { | ||
503 | return (r >> 15) & 0x1; | ||
504 | } | ||
505 | static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) | ||
506 | { | ||
507 | return 0x00000001; | ||
508 | } | ||
509 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_flush_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_flush_gm20b.h new file mode 100644 index 00000000..a6d5e548 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_flush_gm20b.h | |||
@@ -0,0 +1,141 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_flush_gm20b_h_ | ||
51 | #define _hw_flush_gm20b_h_ | ||
52 | |||
53 | static inline u32 flush_l2_system_invalidate_r(void) | ||
54 | { | ||
55 | return 0x00070004; | ||
56 | } | ||
57 | static inline u32 flush_l2_system_invalidate_pending_v(u32 r) | ||
58 | { | ||
59 | return (r >> 0) & 0x1; | ||
60 | } | ||
61 | static inline u32 flush_l2_system_invalidate_pending_busy_v(void) | ||
62 | { | ||
63 | return 0x00000001; | ||
64 | } | ||
65 | static inline u32 flush_l2_system_invalidate_pending_busy_f(void) | ||
66 | { | ||
67 | return 0x1; | ||
68 | } | ||
69 | static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) | ||
70 | { | ||
71 | return (r >> 1) & 0x1; | ||
72 | } | ||
73 | static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) | ||
74 | { | ||
75 | return 0x00000001; | ||
76 | } | ||
77 | static inline u32 flush_l2_flush_dirty_r(void) | ||
78 | { | ||
79 | return 0x00070010; | ||
80 | } | ||
81 | static inline u32 flush_l2_flush_dirty_pending_v(u32 r) | ||
82 | { | ||
83 | return (r >> 0) & 0x1; | ||
84 | } | ||
85 | static inline u32 flush_l2_flush_dirty_pending_empty_v(void) | ||
86 | { | ||
87 | return 0x00000000; | ||
88 | } | ||
89 | static inline u32 flush_l2_flush_dirty_pending_empty_f(void) | ||
90 | { | ||
91 | return 0x0; | ||
92 | } | ||
93 | static inline u32 flush_l2_flush_dirty_pending_busy_v(void) | ||
94 | { | ||
95 | return 0x00000001; | ||
96 | } | ||
97 | static inline u32 flush_l2_flush_dirty_pending_busy_f(void) | ||
98 | { | ||
99 | return 0x1; | ||
100 | } | ||
101 | static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) | ||
102 | { | ||
103 | return (r >> 1) & 0x1; | ||
104 | } | ||
105 | static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) | ||
106 | { | ||
107 | return 0x00000000; | ||
108 | } | ||
109 | static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) | ||
110 | { | ||
111 | return 0x0; | ||
112 | } | ||
113 | static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) | ||
114 | { | ||
115 | return 0x00000001; | ||
116 | } | ||
117 | static inline u32 flush_fb_flush_r(void) | ||
118 | { | ||
119 | return 0x00070000; | ||
120 | } | ||
121 | static inline u32 flush_fb_flush_pending_v(u32 r) | ||
122 | { | ||
123 | return (r >> 0) & 0x1; | ||
124 | } | ||
125 | static inline u32 flush_fb_flush_pending_busy_v(void) | ||
126 | { | ||
127 | return 0x00000001; | ||
128 | } | ||
129 | static inline u32 flush_fb_flush_pending_busy_f(void) | ||
130 | { | ||
131 | return 0x1; | ||
132 | } | ||
133 | static inline u32 flush_fb_flush_outstanding_v(u32 r) | ||
134 | { | ||
135 | return (r >> 1) & 0x1; | ||
136 | } | ||
137 | static inline u32 flush_fb_flush_outstanding_true_v(void) | ||
138 | { | ||
139 | return 0x00000001; | ||
140 | } | ||
141 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h new file mode 100644 index 00000000..e10ce9c8 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_gmmu_gm20b.h | |||
@@ -0,0 +1,1149 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_gmmu_gm20b_h_ | ||
51 | #define _hw_gmmu_gm20b_h_ | ||
52 | |||
53 | static inline u32 gmmu_pde_aperture_big_w(void) | ||
54 | { | ||
55 | return 0; | ||
56 | } | ||
57 | static inline u32 gmmu_pde_aperture_big_invalid_f(void) | ||
58 | { | ||
59 | return 0x0; | ||
60 | } | ||
61 | static inline u32 gmmu_pde_aperture_big_video_memory_f(void) | ||
62 | { | ||
63 | return 0x1; | ||
64 | } | ||
65 | static inline u32 gmmu_pde_size_w(void) | ||
66 | { | ||
67 | return 0; | ||
68 | } | ||
69 | static inline u32 gmmu_pde_size_full_f(void) | ||
70 | { | ||
71 | return 0x0; | ||
72 | } | ||
73 | static inline u32 gmmu_pde_address_big_sys_f(u32 v) | ||
74 | { | ||
75 | return (v & 0xfffffff) << 4; | ||
76 | } | ||
77 | static inline u32 gmmu_pde_address_big_sys_w(void) | ||
78 | { | ||
79 | return 0; | ||
80 | } | ||
81 | static inline u32 gmmu_pde_aperture_small_w(void) | ||
82 | { | ||
83 | return 1; | ||
84 | } | ||
85 | static inline u32 gmmu_pde_aperture_small_invalid_f(void) | ||
86 | { | ||
87 | return 0x0; | ||
88 | } | ||
89 | static inline u32 gmmu_pde_aperture_small_video_memory_f(void) | ||
90 | { | ||
91 | return 0x1; | ||
92 | } | ||
93 | static inline u32 gmmu_pde_vol_small_w(void) | ||
94 | { | ||
95 | return 1; | ||
96 | } | ||
97 | static inline u32 gmmu_pde_vol_small_true_f(void) | ||
98 | { | ||
99 | return 0x4; | ||
100 | } | ||
101 | static inline u32 gmmu_pde_vol_small_false_f(void) | ||
102 | { | ||
103 | return 0x0; | ||
104 | } | ||
105 | static inline u32 gmmu_pde_vol_big_w(void) | ||
106 | { | ||
107 | return 1; | ||
108 | } | ||
109 | static inline u32 gmmu_pde_vol_big_true_f(void) | ||
110 | { | ||
111 | return 0x8; | ||
112 | } | ||
113 | static inline u32 gmmu_pde_vol_big_false_f(void) | ||
114 | { | ||
115 | return 0x0; | ||
116 | } | ||
117 | static inline u32 gmmu_pde_address_small_sys_f(u32 v) | ||
118 | { | ||
119 | return (v & 0xfffffff) << 4; | ||
120 | } | ||
121 | static inline u32 gmmu_pde_address_small_sys_w(void) | ||
122 | { | ||
123 | return 1; | ||
124 | } | ||
125 | static inline u32 gmmu_pde_address_shift_v(void) | ||
126 | { | ||
127 | return 0x0000000c; | ||
128 | } | ||
129 | static inline u32 gmmu_pde__size_v(void) | ||
130 | { | ||
131 | return 0x00000008; | ||
132 | } | ||
133 | static inline u32 gmmu_pte__size_v(void) | ||
134 | { | ||
135 | return 0x00000008; | ||
136 | } | ||
137 | static inline u32 gmmu_pte_valid_w(void) | ||
138 | { | ||
139 | return 0; | ||
140 | } | ||
141 | static inline u32 gmmu_pte_valid_true_f(void) | ||
142 | { | ||
143 | return 0x1; | ||
144 | } | ||
145 | static inline u32 gmmu_pte_address_sys_f(u32 v) | ||
146 | { | ||
147 | return (v & 0xfffffff) << 4; | ||
148 | } | ||
149 | static inline u32 gmmu_pte_address_sys_w(void) | ||
150 | { | ||
151 | return 0; | ||
152 | } | ||
153 | static inline u32 gmmu_pte_vol_w(void) | ||
154 | { | ||
155 | return 1; | ||
156 | } | ||
157 | static inline u32 gmmu_pte_vol_true_f(void) | ||
158 | { | ||
159 | return 0x1; | ||
160 | } | ||
161 | static inline u32 gmmu_pte_vol_false_f(void) | ||
162 | { | ||
163 | return 0x0; | ||
164 | } | ||
165 | static inline u32 gmmu_pte_aperture_w(void) | ||
166 | { | ||
167 | return 1; | ||
168 | } | ||
169 | static inline u32 gmmu_pte_aperture_video_memory_f(void) | ||
170 | { | ||
171 | return 0x0; | ||
172 | } | ||
173 | static inline u32 gmmu_pte_read_only_w(void) | ||
174 | { | ||
175 | return 0; | ||
176 | } | ||
177 | static inline u32 gmmu_pte_read_only_true_f(void) | ||
178 | { | ||
179 | return 0x4; | ||
180 | } | ||
181 | static inline u32 gmmu_pte_write_disable_w(void) | ||
182 | { | ||
183 | return 1; | ||
184 | } | ||
185 | static inline u32 gmmu_pte_write_disable_true_f(void) | ||
186 | { | ||
187 | return 0x80000000; | ||
188 | } | ||
189 | static inline u32 gmmu_pte_read_disable_w(void) | ||
190 | { | ||
191 | return 1; | ||
192 | } | ||
193 | static inline u32 gmmu_pte_read_disable_true_f(void) | ||
194 | { | ||
195 | return 0x40000000; | ||
196 | } | ||
197 | static inline u32 gmmu_pte_comptagline_f(u32 v) | ||
198 | { | ||
199 | return (v & 0x1ffff) << 12; | ||
200 | } | ||
201 | static inline u32 gmmu_pte_comptagline_w(void) | ||
202 | { | ||
203 | return 1; | ||
204 | } | ||
205 | static inline u32 gmmu_pte_address_shift_v(void) | ||
206 | { | ||
207 | return 0x0000000c; | ||
208 | } | ||
209 | static inline u32 gmmu_pte_kind_f(u32 v) | ||
210 | { | ||
211 | return (v & 0xff) << 4; | ||
212 | } | ||
213 | static inline u32 gmmu_pte_kind_w(void) | ||
214 | { | ||
215 | return 1; | ||
216 | } | ||
217 | static inline u32 gmmu_pte_kind_invalid_v(void) | ||
218 | { | ||
219 | return 0x000000ff; | ||
220 | } | ||
221 | static inline u32 gmmu_pte_kind_pitch_v(void) | ||
222 | { | ||
223 | return 0x00000000; | ||
224 | } | ||
225 | static inline u32 gmmu_pte_kind_z16_v(void) | ||
226 | { | ||
227 | return 0x00000001; | ||
228 | } | ||
229 | static inline u32 gmmu_pte_kind_z16_2c_v(void) | ||
230 | { | ||
231 | return 0x00000002; | ||
232 | } | ||
233 | static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) | ||
234 | { | ||
235 | return 0x00000003; | ||
236 | } | ||
237 | static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) | ||
238 | { | ||
239 | return 0x00000004; | ||
240 | } | ||
241 | static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) | ||
242 | { | ||
243 | return 0x00000005; | ||
244 | } | ||
245 | static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) | ||
246 | { | ||
247 | return 0x00000006; | ||
248 | } | ||
249 | static inline u32 gmmu_pte_kind_z16_2z_v(void) | ||
250 | { | ||
251 | return 0x00000007; | ||
252 | } | ||
253 | static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) | ||
254 | { | ||
255 | return 0x00000008; | ||
256 | } | ||
257 | static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) | ||
258 | { | ||
259 | return 0x00000009; | ||
260 | } | ||
261 | static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) | ||
262 | { | ||
263 | return 0x0000000a; | ||
264 | } | ||
265 | static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) | ||
266 | { | ||
267 | return 0x0000000b; | ||
268 | } | ||
269 | static inline u32 gmmu_pte_kind_z16_4cz_v(void) | ||
270 | { | ||
271 | return 0x0000000c; | ||
272 | } | ||
273 | static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) | ||
274 | { | ||
275 | return 0x0000000d; | ||
276 | } | ||
277 | static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) | ||
278 | { | ||
279 | return 0x0000000e; | ||
280 | } | ||
281 | static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) | ||
282 | { | ||
283 | return 0x0000000f; | ||
284 | } | ||
285 | static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) | ||
286 | { | ||
287 | return 0x00000010; | ||
288 | } | ||
289 | static inline u32 gmmu_pte_kind_s8z24_v(void) | ||
290 | { | ||
291 | return 0x00000011; | ||
292 | } | ||
293 | static inline u32 gmmu_pte_kind_s8z24_1z_v(void) | ||
294 | { | ||
295 | return 0x00000012; | ||
296 | } | ||
297 | static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) | ||
298 | { | ||
299 | return 0x00000013; | ||
300 | } | ||
301 | static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) | ||
302 | { | ||
303 | return 0x00000014; | ||
304 | } | ||
305 | static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) | ||
306 | { | ||
307 | return 0x00000015; | ||
308 | } | ||
309 | static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) | ||
310 | { | ||
311 | return 0x00000016; | ||
312 | } | ||
313 | static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) | ||
314 | { | ||
315 | return 0x00000017; | ||
316 | } | ||
317 | static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) | ||
318 | { | ||
319 | return 0x00000018; | ||
320 | } | ||
321 | static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) | ||
322 | { | ||
323 | return 0x00000019; | ||
324 | } | ||
325 | static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) | ||
326 | { | ||
327 | return 0x0000001a; | ||
328 | } | ||
329 | static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) | ||
330 | { | ||
331 | return 0x0000001b; | ||
332 | } | ||
333 | static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) | ||
334 | { | ||
335 | return 0x0000001c; | ||
336 | } | ||
337 | static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) | ||
338 | { | ||
339 | return 0x0000001d; | ||
340 | } | ||
341 | static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) | ||
342 | { | ||
343 | return 0x0000001e; | ||
344 | } | ||
345 | static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) | ||
346 | { | ||
347 | return 0x0000001f; | ||
348 | } | ||
349 | static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) | ||
350 | { | ||
351 | return 0x00000020; | ||
352 | } | ||
353 | static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) | ||
354 | { | ||
355 | return 0x00000021; | ||
356 | } | ||
357 | static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) | ||
358 | { | ||
359 | return 0x00000022; | ||
360 | } | ||
361 | static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) | ||
362 | { | ||
363 | return 0x00000023; | ||
364 | } | ||
365 | static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) | ||
366 | { | ||
367 | return 0x00000024; | ||
368 | } | ||
369 | static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) | ||
370 | { | ||
371 | return 0x00000025; | ||
372 | } | ||
373 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) | ||
374 | { | ||
375 | return 0x00000026; | ||
376 | } | ||
377 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) | ||
378 | { | ||
379 | return 0x00000027; | ||
380 | } | ||
381 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) | ||
382 | { | ||
383 | return 0x00000028; | ||
384 | } | ||
385 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) | ||
386 | { | ||
387 | return 0x00000029; | ||
388 | } | ||
389 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) | ||
390 | { | ||
391 | return 0x0000002e; | ||
392 | } | ||
393 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) | ||
394 | { | ||
395 | return 0x0000002f; | ||
396 | } | ||
397 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) | ||
398 | { | ||
399 | return 0x00000030; | ||
400 | } | ||
401 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) | ||
402 | { | ||
403 | return 0x00000031; | ||
404 | } | ||
405 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) | ||
406 | { | ||
407 | return 0x00000032; | ||
408 | } | ||
409 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) | ||
410 | { | ||
411 | return 0x00000033; | ||
412 | } | ||
413 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) | ||
414 | { | ||
415 | return 0x00000034; | ||
416 | } | ||
417 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) | ||
418 | { | ||
419 | return 0x00000035; | ||
420 | } | ||
421 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) | ||
422 | { | ||
423 | return 0x0000003a; | ||
424 | } | ||
425 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) | ||
426 | { | ||
427 | return 0x0000003b; | ||
428 | } | ||
429 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) | ||
430 | { | ||
431 | return 0x0000003c; | ||
432 | } | ||
433 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) | ||
434 | { | ||
435 | return 0x0000003d; | ||
436 | } | ||
437 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) | ||
438 | { | ||
439 | return 0x0000003e; | ||
440 | } | ||
441 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) | ||
442 | { | ||
443 | return 0x0000003f; | ||
444 | } | ||
445 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) | ||
446 | { | ||
447 | return 0x00000040; | ||
448 | } | ||
449 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) | ||
450 | { | ||
451 | return 0x00000041; | ||
452 | } | ||
453 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) | ||
454 | { | ||
455 | return 0x00000042; | ||
456 | } | ||
457 | static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) | ||
458 | { | ||
459 | return 0x00000043; | ||
460 | } | ||
461 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) | ||
462 | { | ||
463 | return 0x00000044; | ||
464 | } | ||
465 | static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) | ||
466 | { | ||
467 | return 0x00000045; | ||
468 | } | ||
469 | static inline u32 gmmu_pte_kind_z24s8_v(void) | ||
470 | { | ||
471 | return 0x00000046; | ||
472 | } | ||
473 | static inline u32 gmmu_pte_kind_z24s8_1z_v(void) | ||
474 | { | ||
475 | return 0x00000047; | ||
476 | } | ||
477 | static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) | ||
478 | { | ||
479 | return 0x00000048; | ||
480 | } | ||
481 | static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) | ||
482 | { | ||
483 | return 0x00000049; | ||
484 | } | ||
485 | static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) | ||
486 | { | ||
487 | return 0x0000004a; | ||
488 | } | ||
489 | static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) | ||
490 | { | ||
491 | return 0x0000004b; | ||
492 | } | ||
493 | static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) | ||
494 | { | ||
495 | return 0x0000004c; | ||
496 | } | ||
497 | static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) | ||
498 | { | ||
499 | return 0x0000004d; | ||
500 | } | ||
501 | static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) | ||
502 | { | ||
503 | return 0x0000004e; | ||
504 | } | ||
505 | static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) | ||
506 | { | ||
507 | return 0x0000004f; | ||
508 | } | ||
509 | static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) | ||
510 | { | ||
511 | return 0x00000050; | ||
512 | } | ||
513 | static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) | ||
514 | { | ||
515 | return 0x00000051; | ||
516 | } | ||
517 | static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) | ||
518 | { | ||
519 | return 0x00000052; | ||
520 | } | ||
521 | static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) | ||
522 | { | ||
523 | return 0x00000053; | ||
524 | } | ||
525 | static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) | ||
526 | { | ||
527 | return 0x00000054; | ||
528 | } | ||
529 | static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) | ||
530 | { | ||
531 | return 0x00000055; | ||
532 | } | ||
533 | static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) | ||
534 | { | ||
535 | return 0x00000056; | ||
536 | } | ||
537 | static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) | ||
538 | { | ||
539 | return 0x00000057; | ||
540 | } | ||
541 | static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) | ||
542 | { | ||
543 | return 0x00000058; | ||
544 | } | ||
545 | static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) | ||
546 | { | ||
547 | return 0x00000059; | ||
548 | } | ||
549 | static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) | ||
550 | { | ||
551 | return 0x0000005a; | ||
552 | } | ||
553 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) | ||
554 | { | ||
555 | return 0x0000005b; | ||
556 | } | ||
557 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) | ||
558 | { | ||
559 | return 0x0000005c; | ||
560 | } | ||
561 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) | ||
562 | { | ||
563 | return 0x0000005d; | ||
564 | } | ||
565 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) | ||
566 | { | ||
567 | return 0x0000005e; | ||
568 | } | ||
569 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) | ||
570 | { | ||
571 | return 0x00000063; | ||
572 | } | ||
573 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) | ||
574 | { | ||
575 | return 0x00000064; | ||
576 | } | ||
577 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) | ||
578 | { | ||
579 | return 0x00000065; | ||
580 | } | ||
581 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) | ||
582 | { | ||
583 | return 0x00000066; | ||
584 | } | ||
585 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) | ||
586 | { | ||
587 | return 0x00000067; | ||
588 | } | ||
589 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) | ||
590 | { | ||
591 | return 0x00000068; | ||
592 | } | ||
593 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) | ||
594 | { | ||
595 | return 0x00000069; | ||
596 | } | ||
597 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) | ||
598 | { | ||
599 | return 0x0000006a; | ||
600 | } | ||
601 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) | ||
602 | { | ||
603 | return 0x0000006f; | ||
604 | } | ||
605 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) | ||
606 | { | ||
607 | return 0x00000070; | ||
608 | } | ||
609 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) | ||
610 | { | ||
611 | return 0x00000071; | ||
612 | } | ||
613 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) | ||
614 | { | ||
615 | return 0x00000072; | ||
616 | } | ||
617 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) | ||
618 | { | ||
619 | return 0x00000073; | ||
620 | } | ||
621 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) | ||
622 | { | ||
623 | return 0x00000074; | ||
624 | } | ||
625 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) | ||
626 | { | ||
627 | return 0x00000075; | ||
628 | } | ||
629 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) | ||
630 | { | ||
631 | return 0x00000076; | ||
632 | } | ||
633 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) | ||
634 | { | ||
635 | return 0x00000077; | ||
636 | } | ||
637 | static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) | ||
638 | { | ||
639 | return 0x00000078; | ||
640 | } | ||
641 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) | ||
642 | { | ||
643 | return 0x00000079; | ||
644 | } | ||
645 | static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) | ||
646 | { | ||
647 | return 0x0000007a; | ||
648 | } | ||
649 | static inline u32 gmmu_pte_kind_zf32_v(void) | ||
650 | { | ||
651 | return 0x0000007b; | ||
652 | } | ||
653 | static inline u32 gmmu_pte_kind_zf32_1z_v(void) | ||
654 | { | ||
655 | return 0x0000007c; | ||
656 | } | ||
657 | static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) | ||
658 | { | ||
659 | return 0x0000007d; | ||
660 | } | ||
661 | static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) | ||
662 | { | ||
663 | return 0x0000007e; | ||
664 | } | ||
665 | static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) | ||
666 | { | ||
667 | return 0x0000007f; | ||
668 | } | ||
669 | static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) | ||
670 | { | ||
671 | return 0x00000080; | ||
672 | } | ||
673 | static inline u32 gmmu_pte_kind_zf32_2cs_v(void) | ||
674 | { | ||
675 | return 0x00000081; | ||
676 | } | ||
677 | static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) | ||
678 | { | ||
679 | return 0x00000082; | ||
680 | } | ||
681 | static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) | ||
682 | { | ||
683 | return 0x00000083; | ||
684 | } | ||
685 | static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) | ||
686 | { | ||
687 | return 0x00000084; | ||
688 | } | ||
689 | static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) | ||
690 | { | ||
691 | return 0x00000085; | ||
692 | } | ||
693 | static inline u32 gmmu_pte_kind_zf32_2cz_v(void) | ||
694 | { | ||
695 | return 0x00000086; | ||
696 | } | ||
697 | static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) | ||
698 | { | ||
699 | return 0x00000087; | ||
700 | } | ||
701 | static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) | ||
702 | { | ||
703 | return 0x00000088; | ||
704 | } | ||
705 | static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) | ||
706 | { | ||
707 | return 0x00000089; | ||
708 | } | ||
709 | static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) | ||
710 | { | ||
711 | return 0x0000008a; | ||
712 | } | ||
713 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) | ||
714 | { | ||
715 | return 0x0000008b; | ||
716 | } | ||
717 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) | ||
718 | { | ||
719 | return 0x0000008c; | ||
720 | } | ||
721 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) | ||
722 | { | ||
723 | return 0x0000008d; | ||
724 | } | ||
725 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) | ||
726 | { | ||
727 | return 0x0000008e; | ||
728 | } | ||
729 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) | ||
730 | { | ||
731 | return 0x0000008f; | ||
732 | } | ||
733 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) | ||
734 | { | ||
735 | return 0x00000090; | ||
736 | } | ||
737 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) | ||
738 | { | ||
739 | return 0x00000091; | ||
740 | } | ||
741 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) | ||
742 | { | ||
743 | return 0x00000092; | ||
744 | } | ||
745 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) | ||
746 | { | ||
747 | return 0x00000097; | ||
748 | } | ||
749 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) | ||
750 | { | ||
751 | return 0x00000098; | ||
752 | } | ||
753 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) | ||
754 | { | ||
755 | return 0x00000099; | ||
756 | } | ||
757 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) | ||
758 | { | ||
759 | return 0x0000009a; | ||
760 | } | ||
761 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) | ||
762 | { | ||
763 | return 0x0000009b; | ||
764 | } | ||
765 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) | ||
766 | { | ||
767 | return 0x0000009c; | ||
768 | } | ||
769 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) | ||
770 | { | ||
771 | return 0x0000009d; | ||
772 | } | ||
773 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) | ||
774 | { | ||
775 | return 0x0000009e; | ||
776 | } | ||
777 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) | ||
778 | { | ||
779 | return 0x0000009f; | ||
780 | } | ||
781 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) | ||
782 | { | ||
783 | return 0x000000a0; | ||
784 | } | ||
785 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) | ||
786 | { | ||
787 | return 0x000000a1; | ||
788 | } | ||
789 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) | ||
790 | { | ||
791 | return 0x000000a2; | ||
792 | } | ||
793 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) | ||
794 | { | ||
795 | return 0x000000a3; | ||
796 | } | ||
797 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) | ||
798 | { | ||
799 | return 0x000000a4; | ||
800 | } | ||
801 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) | ||
802 | { | ||
803 | return 0x000000a5; | ||
804 | } | ||
805 | static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) | ||
806 | { | ||
807 | return 0x000000a6; | ||
808 | } | ||
809 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) | ||
810 | { | ||
811 | return 0x000000a7; | ||
812 | } | ||
813 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) | ||
814 | { | ||
815 | return 0x000000a8; | ||
816 | } | ||
817 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) | ||
818 | { | ||
819 | return 0x000000a9; | ||
820 | } | ||
821 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) | ||
822 | { | ||
823 | return 0x000000aa; | ||
824 | } | ||
825 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) | ||
826 | { | ||
827 | return 0x000000ab; | ||
828 | } | ||
829 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) | ||
830 | { | ||
831 | return 0x000000ac; | ||
832 | } | ||
833 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) | ||
834 | { | ||
835 | return 0x000000ad; | ||
836 | } | ||
837 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) | ||
838 | { | ||
839 | return 0x000000ae; | ||
840 | } | ||
841 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) | ||
842 | { | ||
843 | return 0x000000b3; | ||
844 | } | ||
845 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) | ||
846 | { | ||
847 | return 0x000000b4; | ||
848 | } | ||
849 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) | ||
850 | { | ||
851 | return 0x000000b5; | ||
852 | } | ||
853 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) | ||
854 | { | ||
855 | return 0x000000b6; | ||
856 | } | ||
857 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) | ||
858 | { | ||
859 | return 0x000000b7; | ||
860 | } | ||
861 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) | ||
862 | { | ||
863 | return 0x000000b8; | ||
864 | } | ||
865 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) | ||
866 | { | ||
867 | return 0x000000b9; | ||
868 | } | ||
869 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) | ||
870 | { | ||
871 | return 0x000000ba; | ||
872 | } | ||
873 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) | ||
874 | { | ||
875 | return 0x000000bb; | ||
876 | } | ||
877 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) | ||
878 | { | ||
879 | return 0x000000bc; | ||
880 | } | ||
881 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) | ||
882 | { | ||
883 | return 0x000000bd; | ||
884 | } | ||
885 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) | ||
886 | { | ||
887 | return 0x000000be; | ||
888 | } | ||
889 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) | ||
890 | { | ||
891 | return 0x000000bf; | ||
892 | } | ||
893 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) | ||
894 | { | ||
895 | return 0x000000c0; | ||
896 | } | ||
897 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) | ||
898 | { | ||
899 | return 0x000000c1; | ||
900 | } | ||
901 | static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) | ||
902 | { | ||
903 | return 0x000000c2; | ||
904 | } | ||
905 | static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) | ||
906 | { | ||
907 | return 0x000000c3; | ||
908 | } | ||
909 | static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) | ||
910 | { | ||
911 | return 0x000000c4; | ||
912 | } | ||
913 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) | ||
914 | { | ||
915 | return 0x000000c5; | ||
916 | } | ||
917 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) | ||
918 | { | ||
919 | return 0x000000c6; | ||
920 | } | ||
921 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) | ||
922 | { | ||
923 | return 0x000000c7; | ||
924 | } | ||
925 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) | ||
926 | { | ||
927 | return 0x000000c8; | ||
928 | } | ||
929 | static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) | ||
930 | { | ||
931 | return 0x000000ce; | ||
932 | } | ||
933 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) | ||
934 | { | ||
935 | return 0x000000cf; | ||
936 | } | ||
937 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) | ||
938 | { | ||
939 | return 0x000000d0; | ||
940 | } | ||
941 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) | ||
942 | { | ||
943 | return 0x000000d1; | ||
944 | } | ||
945 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) | ||
946 | { | ||
947 | return 0x000000d2; | ||
948 | } | ||
949 | static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) | ||
950 | { | ||
951 | return 0x000000d3; | ||
952 | } | ||
953 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) | ||
954 | { | ||
955 | return 0x000000d4; | ||
956 | } | ||
957 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) | ||
958 | { | ||
959 | return 0x000000d5; | ||
960 | } | ||
961 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) | ||
962 | { | ||
963 | return 0x000000d6; | ||
964 | } | ||
965 | static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) | ||
966 | { | ||
967 | return 0x000000d7; | ||
968 | } | ||
969 | static inline u32 gmmu_pte_kind_generic_16bx2_v(void) | ||
970 | { | ||
971 | return 0x000000fe; | ||
972 | } | ||
973 | static inline u32 gmmu_pte_kind_c32_2c_v(void) | ||
974 | { | ||
975 | return 0x000000d8; | ||
976 | } | ||
977 | static inline u32 gmmu_pte_kind_c32_2cbr_v(void) | ||
978 | { | ||
979 | return 0x000000d9; | ||
980 | } | ||
981 | static inline u32 gmmu_pte_kind_c32_2cba_v(void) | ||
982 | { | ||
983 | return 0x000000da; | ||
984 | } | ||
985 | static inline u32 gmmu_pte_kind_c32_2cra_v(void) | ||
986 | { | ||
987 | return 0x000000db; | ||
988 | } | ||
989 | static inline u32 gmmu_pte_kind_c32_2bra_v(void) | ||
990 | { | ||
991 | return 0x000000dc; | ||
992 | } | ||
993 | static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) | ||
994 | { | ||
995 | return 0x000000dd; | ||
996 | } | ||
997 | static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) | ||
998 | { | ||
999 | return 0x000000de; | ||
1000 | } | ||
1001 | static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) | ||
1002 | { | ||
1003 | return 0x000000cc; | ||
1004 | } | ||
1005 | static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) | ||
1006 | { | ||
1007 | return 0x000000df; | ||
1008 | } | ||
1009 | static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) | ||
1010 | { | ||
1011 | return 0x000000e0; | ||
1012 | } | ||
1013 | static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) | ||
1014 | { | ||
1015 | return 0x000000e1; | ||
1016 | } | ||
1017 | static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) | ||
1018 | { | ||
1019 | return 0x000000e2; | ||
1020 | } | ||
1021 | static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) | ||
1022 | { | ||
1023 | return 0x000000e3; | ||
1024 | } | ||
1025 | static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) | ||
1026 | { | ||
1027 | return 0x000000e4; | ||
1028 | } | ||
1029 | static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) | ||
1030 | { | ||
1031 | return 0x000000e5; | ||
1032 | } | ||
1033 | static inline u32 gmmu_pte_kind_c64_2c_v(void) | ||
1034 | { | ||
1035 | return 0x000000e6; | ||
1036 | } | ||
1037 | static inline u32 gmmu_pte_kind_c64_2cbr_v(void) | ||
1038 | { | ||
1039 | return 0x000000e7; | ||
1040 | } | ||
1041 | static inline u32 gmmu_pte_kind_c64_2cba_v(void) | ||
1042 | { | ||
1043 | return 0x000000e8; | ||
1044 | } | ||
1045 | static inline u32 gmmu_pte_kind_c64_2cra_v(void) | ||
1046 | { | ||
1047 | return 0x000000e9; | ||
1048 | } | ||
1049 | static inline u32 gmmu_pte_kind_c64_2bra_v(void) | ||
1050 | { | ||
1051 | return 0x000000ea; | ||
1052 | } | ||
1053 | static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) | ||
1054 | { | ||
1055 | return 0x000000eb; | ||
1056 | } | ||
1057 | static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) | ||
1058 | { | ||
1059 | return 0x000000ec; | ||
1060 | } | ||
1061 | static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) | ||
1062 | { | ||
1063 | return 0x000000cd; | ||
1064 | } | ||
1065 | static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) | ||
1066 | { | ||
1067 | return 0x000000ed; | ||
1068 | } | ||
1069 | static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) | ||
1070 | { | ||
1071 | return 0x000000ee; | ||
1072 | } | ||
1073 | static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) | ||
1074 | { | ||
1075 | return 0x000000ef; | ||
1076 | } | ||
1077 | static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) | ||
1078 | { | ||
1079 | return 0x000000f0; | ||
1080 | } | ||
1081 | static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) | ||
1082 | { | ||
1083 | return 0x000000f1; | ||
1084 | } | ||
1085 | static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) | ||
1086 | { | ||
1087 | return 0x000000f2; | ||
1088 | } | ||
1089 | static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) | ||
1090 | { | ||
1091 | return 0x000000f3; | ||
1092 | } | ||
1093 | static inline u32 gmmu_pte_kind_c128_2c_v(void) | ||
1094 | { | ||
1095 | return 0x000000f4; | ||
1096 | } | ||
1097 | static inline u32 gmmu_pte_kind_c128_2cr_v(void) | ||
1098 | { | ||
1099 | return 0x000000f5; | ||
1100 | } | ||
1101 | static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) | ||
1102 | { | ||
1103 | return 0x000000f6; | ||
1104 | } | ||
1105 | static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) | ||
1106 | { | ||
1107 | return 0x000000f7; | ||
1108 | } | ||
1109 | static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) | ||
1110 | { | ||
1111 | return 0x000000f8; | ||
1112 | } | ||
1113 | static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) | ||
1114 | { | ||
1115 | return 0x000000f9; | ||
1116 | } | ||
1117 | static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) | ||
1118 | { | ||
1119 | return 0x000000fa; | ||
1120 | } | ||
1121 | static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) | ||
1122 | { | ||
1123 | return 0x000000fb; | ||
1124 | } | ||
1125 | static inline u32 gmmu_pte_kind_x8c24_v(void) | ||
1126 | { | ||
1127 | return 0x000000fc; | ||
1128 | } | ||
1129 | static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) | ||
1130 | { | ||
1131 | return 0x000000fd; | ||
1132 | } | ||
1133 | static inline u32 gmmu_pte_kind_smsked_message_v(void) | ||
1134 | { | ||
1135 | return 0x000000ca; | ||
1136 | } | ||
1137 | static inline u32 gmmu_pte_kind_smhost_message_v(void) | ||
1138 | { | ||
1139 | return 0x000000cb; | ||
1140 | } | ||
1141 | static inline u32 gmmu_pte_kind_s8_v(void) | ||
1142 | { | ||
1143 | return 0x0000002a; | ||
1144 | } | ||
1145 | static inline u32 gmmu_pte_kind_s8_2s_v(void) | ||
1146 | { | ||
1147 | return 0x0000002b; | ||
1148 | } | ||
1149 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h new file mode 100644 index 00000000..a4ae1ec0 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -0,0 +1,3217 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_gr_gm20b_h_ | ||
51 | #define _hw_gr_gm20b_h_ | ||
52 | |||
53 | static inline u32 gr_intr_r(void) | ||
54 | { | ||
55 | return 0x00400100; | ||
56 | } | ||
57 | static inline u32 gr_intr_notify_pending_f(void) | ||
58 | { | ||
59 | return 0x1; | ||
60 | } | ||
61 | static inline u32 gr_intr_notify_reset_f(void) | ||
62 | { | ||
63 | return 0x1; | ||
64 | } | ||
65 | static inline u32 gr_intr_semaphore_pending_f(void) | ||
66 | { | ||
67 | return 0x2; | ||
68 | } | ||
69 | static inline u32 gr_intr_semaphore_reset_f(void) | ||
70 | { | ||
71 | return 0x2; | ||
72 | } | ||
73 | static inline u32 gr_intr_illegal_method_pending_f(void) | ||
74 | { | ||
75 | return 0x10; | ||
76 | } | ||
77 | static inline u32 gr_intr_illegal_method_reset_f(void) | ||
78 | { | ||
79 | return 0x10; | ||
80 | } | ||
81 | static inline u32 gr_intr_illegal_class_pending_f(void) | ||
82 | { | ||
83 | return 0x20; | ||
84 | } | ||
85 | static inline u32 gr_intr_illegal_class_reset_f(void) | ||
86 | { | ||
87 | return 0x20; | ||
88 | } | ||
89 | static inline u32 gr_intr_class_error_pending_f(void) | ||
90 | { | ||
91 | return 0x100000; | ||
92 | } | ||
93 | static inline u32 gr_intr_class_error_reset_f(void) | ||
94 | { | ||
95 | return 0x100000; | ||
96 | } | ||
97 | static inline u32 gr_intr_exception_pending_f(void) | ||
98 | { | ||
99 | return 0x200000; | ||
100 | } | ||
101 | static inline u32 gr_intr_exception_reset_f(void) | ||
102 | { | ||
103 | return 0x200000; | ||
104 | } | ||
105 | static inline u32 gr_intr_en_r(void) | ||
106 | { | ||
107 | return 0x0040013c; | ||
108 | } | ||
109 | static inline u32 gr_exception_r(void) | ||
110 | { | ||
111 | return 0x00400108; | ||
112 | } | ||
113 | static inline u32 gr_exception_fe_m(void) | ||
114 | { | ||
115 | return 0x1 << 0; | ||
116 | } | ||
117 | static inline u32 gr_exception_gpc_m(void) | ||
118 | { | ||
119 | return 0x1 << 24; | ||
120 | } | ||
121 | static inline u32 gr_exception1_r(void) | ||
122 | { | ||
123 | return 0x00400118; | ||
124 | } | ||
125 | static inline u32 gr_exception1_gpc_0_pending_f(void) | ||
126 | { | ||
127 | return 0x1; | ||
128 | } | ||
129 | static inline u32 gr_exception2_r(void) | ||
130 | { | ||
131 | return 0x0040011c; | ||
132 | } | ||
133 | static inline u32 gr_exception_en_r(void) | ||
134 | { | ||
135 | return 0x00400138; | ||
136 | } | ||
137 | static inline u32 gr_exception_en_fe_m(void) | ||
138 | { | ||
139 | return 0x1 << 0; | ||
140 | } | ||
141 | static inline u32 gr_exception1_en_r(void) | ||
142 | { | ||
143 | return 0x00400130; | ||
144 | } | ||
145 | static inline u32 gr_exception2_en_r(void) | ||
146 | { | ||
147 | return 0x00400134; | ||
148 | } | ||
149 | static inline u32 gr_gpfifo_ctl_r(void) | ||
150 | { | ||
151 | return 0x00400500; | ||
152 | } | ||
153 | static inline u32 gr_gpfifo_ctl_access_f(u32 v) | ||
154 | { | ||
155 | return (v & 0x1) << 0; | ||
156 | } | ||
157 | static inline u32 gr_gpfifo_ctl_access_disabled_f(void) | ||
158 | { | ||
159 | return 0x0; | ||
160 | } | ||
161 | static inline u32 gr_gpfifo_ctl_access_enabled_f(void) | ||
162 | { | ||
163 | return 0x1; | ||
164 | } | ||
165 | static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) | ||
166 | { | ||
167 | return (v & 0x1) << 16; | ||
168 | } | ||
169 | static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) | ||
170 | { | ||
171 | return 0x00000001; | ||
172 | } | ||
173 | static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) | ||
174 | { | ||
175 | return 0x10000; | ||
176 | } | ||
177 | static inline u32 gr_trapped_addr_r(void) | ||
178 | { | ||
179 | return 0x00400704; | ||
180 | } | ||
181 | static inline u32 gr_trapped_addr_mthd_v(u32 r) | ||
182 | { | ||
183 | return (r >> 2) & 0xfff; | ||
184 | } | ||
185 | static inline u32 gr_trapped_addr_subch_v(u32 r) | ||
186 | { | ||
187 | return (r >> 16) & 0x7; | ||
188 | } | ||
189 | static inline u32 gr_trapped_data_lo_r(void) | ||
190 | { | ||
191 | return 0x00400708; | ||
192 | } | ||
193 | static inline u32 gr_trapped_data_hi_r(void) | ||
194 | { | ||
195 | return 0x0040070c; | ||
196 | } | ||
197 | static inline u32 gr_status_r(void) | ||
198 | { | ||
199 | return 0x00400700; | ||
200 | } | ||
201 | static inline u32 gr_status_fe_method_lower_v(u32 r) | ||
202 | { | ||
203 | return (r >> 2) & 0x1; | ||
204 | } | ||
205 | static inline u32 gr_status_fe_method_lower_idle_v(void) | ||
206 | { | ||
207 | return 0x00000000; | ||
208 | } | ||
209 | static inline u32 gr_status_mask_r(void) | ||
210 | { | ||
211 | return 0x00400610; | ||
212 | } | ||
213 | static inline u32 gr_engine_status_r(void) | ||
214 | { | ||
215 | return 0x0040060c; | ||
216 | } | ||
217 | static inline u32 gr_engine_status_value_busy_f(void) | ||
218 | { | ||
219 | return 0x1; | ||
220 | } | ||
221 | static inline u32 gr_pipe_bundle_address_r(void) | ||
222 | { | ||
223 | return 0x00400200; | ||
224 | } | ||
225 | static inline u32 gr_pipe_bundle_address_value_v(u32 r) | ||
226 | { | ||
227 | return (r >> 0) & 0xffff; | ||
228 | } | ||
229 | static inline u32 gr_pipe_bundle_data_r(void) | ||
230 | { | ||
231 | return 0x00400204; | ||
232 | } | ||
233 | static inline u32 gr_pipe_bundle_config_r(void) | ||
234 | { | ||
235 | return 0x00400208; | ||
236 | } | ||
237 | static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) | ||
238 | { | ||
239 | return 0x0; | ||
240 | } | ||
241 | static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) | ||
242 | { | ||
243 | return 0x80000000; | ||
244 | } | ||
245 | static inline u32 gr_fe_hww_esr_r(void) | ||
246 | { | ||
247 | return 0x00404000; | ||
248 | } | ||
249 | static inline u32 gr_fe_hww_esr_reset_active_f(void) | ||
250 | { | ||
251 | return 0x40000000; | ||
252 | } | ||
253 | static inline u32 gr_fe_hww_esr_en_enable_f(void) | ||
254 | { | ||
255 | return 0x80000000; | ||
256 | } | ||
257 | static inline u32 gr_fe_go_idle_timeout_r(void) | ||
258 | { | ||
259 | return 0x00404154; | ||
260 | } | ||
261 | static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) | ||
262 | { | ||
263 | return (v & 0xffffffff) << 0; | ||
264 | } | ||
265 | static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) | ||
266 | { | ||
267 | return 0x0; | ||
268 | } | ||
269 | static inline u32 gr_fe_object_table_r(u32 i) | ||
270 | { | ||
271 | return 0x00404200 + i*4; | ||
272 | } | ||
273 | static inline u32 gr_fe_object_table_nvclass_v(u32 r) | ||
274 | { | ||
275 | return (r >> 0) & 0xffff; | ||
276 | } | ||
277 | static inline u32 gr_fe_tpc_fs_r(void) | ||
278 | { | ||
279 | return 0x004041c4; | ||
280 | } | ||
281 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) | ||
282 | { | ||
283 | return 0x00404488; | ||
284 | } | ||
285 | static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) | ||
286 | { | ||
287 | return 0x80000000; | ||
288 | } | ||
289 | static inline u32 gr_pri_mme_shadow_raw_data_r(void) | ||
290 | { | ||
291 | return 0x0040448c; | ||
292 | } | ||
293 | static inline u32 gr_mme_hww_esr_r(void) | ||
294 | { | ||
295 | return 0x00404490; | ||
296 | } | ||
297 | static inline u32 gr_mme_hww_esr_reset_active_f(void) | ||
298 | { | ||
299 | return 0x40000000; | ||
300 | } | ||
301 | static inline u32 gr_mme_hww_esr_en_enable_f(void) | ||
302 | { | ||
303 | return 0x80000000; | ||
304 | } | ||
305 | static inline u32 gr_memfmt_hww_esr_r(void) | ||
306 | { | ||
307 | return 0x00404600; | ||
308 | } | ||
309 | static inline u32 gr_memfmt_hww_esr_reset_active_f(void) | ||
310 | { | ||
311 | return 0x40000000; | ||
312 | } | ||
313 | static inline u32 gr_memfmt_hww_esr_en_enable_f(void) | ||
314 | { | ||
315 | return 0x80000000; | ||
316 | } | ||
317 | static inline u32 gr_fecs_cpuctl_r(void) | ||
318 | { | ||
319 | return 0x00409100; | ||
320 | } | ||
321 | static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) | ||
322 | { | ||
323 | return (v & 0x1) << 1; | ||
324 | } | ||
325 | static inline u32 gr_fecs_dmactl_r(void) | ||
326 | { | ||
327 | return 0x0040910c; | ||
328 | } | ||
329 | static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) | ||
330 | { | ||
331 | return (v & 0x1) << 0; | ||
332 | } | ||
333 | static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) | ||
334 | { | ||
335 | return 0x1 << 1; | ||
336 | } | ||
337 | static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) | ||
338 | { | ||
339 | return 0x1 << 2; | ||
340 | } | ||
341 | static inline u32 gr_fecs_os_r(void) | ||
342 | { | ||
343 | return 0x00409080; | ||
344 | } | ||
345 | static inline u32 gr_fecs_idlestate_r(void) | ||
346 | { | ||
347 | return 0x0040904c; | ||
348 | } | ||
349 | static inline u32 gr_fecs_mailbox0_r(void) | ||
350 | { | ||
351 | return 0x00409040; | ||
352 | } | ||
353 | static inline u32 gr_fecs_mailbox1_r(void) | ||
354 | { | ||
355 | return 0x00409044; | ||
356 | } | ||
357 | static inline u32 gr_fecs_irqstat_r(void) | ||
358 | { | ||
359 | return 0x00409008; | ||
360 | } | ||
361 | static inline u32 gr_fecs_irqmode_r(void) | ||
362 | { | ||
363 | return 0x0040900c; | ||
364 | } | ||
365 | static inline u32 gr_fecs_irqmask_r(void) | ||
366 | { | ||
367 | return 0x00409018; | ||
368 | } | ||
369 | static inline u32 gr_fecs_irqdest_r(void) | ||
370 | { | ||
371 | return 0x0040901c; | ||
372 | } | ||
373 | static inline u32 gr_fecs_curctx_r(void) | ||
374 | { | ||
375 | return 0x00409050; | ||
376 | } | ||
377 | static inline u32 gr_fecs_nxtctx_r(void) | ||
378 | { | ||
379 | return 0x00409054; | ||
380 | } | ||
381 | static inline u32 gr_fecs_engctl_r(void) | ||
382 | { | ||
383 | return 0x004090a4; | ||
384 | } | ||
385 | static inline u32 gr_fecs_debug1_r(void) | ||
386 | { | ||
387 | return 0x00409090; | ||
388 | } | ||
389 | static inline u32 gr_fecs_debuginfo_r(void) | ||
390 | { | ||
391 | return 0x00409094; | ||
392 | } | ||
393 | static inline u32 gr_fecs_icd_cmd_r(void) | ||
394 | { | ||
395 | return 0x00409200; | ||
396 | } | ||
397 | static inline u32 gr_fecs_icd_cmd_opc_s(void) | ||
398 | { | ||
399 | return 4; | ||
400 | } | ||
401 | static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) | ||
402 | { | ||
403 | return (v & 0xf) << 0; | ||
404 | } | ||
405 | static inline u32 gr_fecs_icd_cmd_opc_m(void) | ||
406 | { | ||
407 | return 0xf << 0; | ||
408 | } | ||
409 | static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) | ||
410 | { | ||
411 | return (r >> 0) & 0xf; | ||
412 | } | ||
413 | static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) | ||
414 | { | ||
415 | return 0x8; | ||
416 | } | ||
417 | static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) | ||
418 | { | ||
419 | return 0xe; | ||
420 | } | ||
421 | static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) | ||
422 | { | ||
423 | return (v & 0x1f) << 8; | ||
424 | } | ||
425 | static inline u32 gr_fecs_icd_rdata_r(void) | ||
426 | { | ||
427 | return 0x0040920c; | ||
428 | } | ||
429 | static inline u32 gr_fecs_imemc_r(u32 i) | ||
430 | { | ||
431 | return 0x00409180 + i*16; | ||
432 | } | ||
433 | static inline u32 gr_fecs_imemc_offs_f(u32 v) | ||
434 | { | ||
435 | return (v & 0x3f) << 2; | ||
436 | } | ||
437 | static inline u32 gr_fecs_imemc_blk_f(u32 v) | ||
438 | { | ||
439 | return (v & 0xff) << 8; | ||
440 | } | ||
441 | static inline u32 gr_fecs_imemc_aincw_f(u32 v) | ||
442 | { | ||
443 | return (v & 0x1) << 24; | ||
444 | } | ||
445 | static inline u32 gr_fecs_imemd_r(u32 i) | ||
446 | { | ||
447 | return 0x00409184 + i*16; | ||
448 | } | ||
449 | static inline u32 gr_fecs_imemt_r(u32 i) | ||
450 | { | ||
451 | return 0x00409188 + i*16; | ||
452 | } | ||
453 | static inline u32 gr_fecs_imemt_tag_f(u32 v) | ||
454 | { | ||
455 | return (v & 0xffff) << 0; | ||
456 | } | ||
457 | static inline u32 gr_fecs_dmemc_r(u32 i) | ||
458 | { | ||
459 | return 0x004091c0 + i*8; | ||
460 | } | ||
461 | static inline u32 gr_fecs_dmemc_offs_s(void) | ||
462 | { | ||
463 | return 6; | ||
464 | } | ||
465 | static inline u32 gr_fecs_dmemc_offs_f(u32 v) | ||
466 | { | ||
467 | return (v & 0x3f) << 2; | ||
468 | } | ||
469 | static inline u32 gr_fecs_dmemc_offs_m(void) | ||
470 | { | ||
471 | return 0x3f << 2; | ||
472 | } | ||
473 | static inline u32 gr_fecs_dmemc_offs_v(u32 r) | ||
474 | { | ||
475 | return (r >> 2) & 0x3f; | ||
476 | } | ||
477 | static inline u32 gr_fecs_dmemc_blk_f(u32 v) | ||
478 | { | ||
479 | return (v & 0xff) << 8; | ||
480 | } | ||
481 | static inline u32 gr_fecs_dmemc_aincw_f(u32 v) | ||
482 | { | ||
483 | return (v & 0x1) << 24; | ||
484 | } | ||
485 | static inline u32 gr_fecs_dmemd_r(u32 i) | ||
486 | { | ||
487 | return 0x004091c4 + i*8; | ||
488 | } | ||
489 | static inline u32 gr_fecs_dmatrfbase_r(void) | ||
490 | { | ||
491 | return 0x00409110; | ||
492 | } | ||
493 | static inline u32 gr_fecs_dmatrfmoffs_r(void) | ||
494 | { | ||
495 | return 0x00409114; | ||
496 | } | ||
497 | static inline u32 gr_fecs_dmatrffboffs_r(void) | ||
498 | { | ||
499 | return 0x0040911c; | ||
500 | } | ||
501 | static inline u32 gr_fecs_dmatrfcmd_r(void) | ||
502 | { | ||
503 | return 0x00409118; | ||
504 | } | ||
505 | static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) | ||
506 | { | ||
507 | return (v & 0x1) << 4; | ||
508 | } | ||
509 | static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) | ||
510 | { | ||
511 | return (v & 0x1) << 5; | ||
512 | } | ||
513 | static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) | ||
514 | { | ||
515 | return (v & 0x7) << 8; | ||
516 | } | ||
517 | static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) | ||
518 | { | ||
519 | return (v & 0x7) << 12; | ||
520 | } | ||
521 | static inline u32 gr_fecs_bootvec_r(void) | ||
522 | { | ||
523 | return 0x00409104; | ||
524 | } | ||
525 | static inline u32 gr_fecs_bootvec_vec_f(u32 v) | ||
526 | { | ||
527 | return (v & 0xffffffff) << 0; | ||
528 | } | ||
529 | static inline u32 gr_fecs_falcon_hwcfg_r(void) | ||
530 | { | ||
531 | return 0x00409108; | ||
532 | } | ||
533 | static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) | ||
534 | { | ||
535 | return 0x0041a108; | ||
536 | } | ||
537 | static inline u32 gr_fecs_falcon_rm_r(void) | ||
538 | { | ||
539 | return 0x00409084; | ||
540 | } | ||
541 | static inline u32 gr_fecs_current_ctx_r(void) | ||
542 | { | ||
543 | return 0x00409b00; | ||
544 | } | ||
545 | static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) | ||
546 | { | ||
547 | return (v & 0xfffffff) << 0; | ||
548 | } | ||
549 | static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) | ||
550 | { | ||
551 | return (r >> 0) & 0xfffffff; | ||
552 | } | ||
553 | static inline u32 gr_fecs_current_ctx_target_s(void) | ||
554 | { | ||
555 | return 2; | ||
556 | } | ||
557 | static inline u32 gr_fecs_current_ctx_target_f(u32 v) | ||
558 | { | ||
559 | return (v & 0x3) << 28; | ||
560 | } | ||
561 | static inline u32 gr_fecs_current_ctx_target_m(void) | ||
562 | { | ||
563 | return 0x3 << 28; | ||
564 | } | ||
565 | static inline u32 gr_fecs_current_ctx_target_v(u32 r) | ||
566 | { | ||
567 | return (r >> 28) & 0x3; | ||
568 | } | ||
569 | static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) | ||
570 | { | ||
571 | return 0x0; | ||
572 | } | ||
573 | static inline u32 gr_fecs_current_ctx_valid_s(void) | ||
574 | { | ||
575 | return 1; | ||
576 | } | ||
577 | static inline u32 gr_fecs_current_ctx_valid_f(u32 v) | ||
578 | { | ||
579 | return (v & 0x1) << 31; | ||
580 | } | ||
581 | static inline u32 gr_fecs_current_ctx_valid_m(void) | ||
582 | { | ||
583 | return 0x1 << 31; | ||
584 | } | ||
585 | static inline u32 gr_fecs_current_ctx_valid_v(u32 r) | ||
586 | { | ||
587 | return (r >> 31) & 0x1; | ||
588 | } | ||
589 | static inline u32 gr_fecs_current_ctx_valid_false_f(void) | ||
590 | { | ||
591 | return 0x0; | ||
592 | } | ||
593 | static inline u32 gr_fecs_method_data_r(void) | ||
594 | { | ||
595 | return 0x00409500; | ||
596 | } | ||
597 | static inline u32 gr_fecs_method_push_r(void) | ||
598 | { | ||
599 | return 0x00409504; | ||
600 | } | ||
601 | static inline u32 gr_fecs_method_push_adr_f(u32 v) | ||
602 | { | ||
603 | return (v & 0xfff) << 0; | ||
604 | } | ||
605 | static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) | ||
606 | { | ||
607 | return 0x00000003; | ||
608 | } | ||
609 | static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) | ||
610 | { | ||
611 | return 0x3; | ||
612 | } | ||
613 | static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) | ||
614 | { | ||
615 | return 0x00000010; | ||
616 | } | ||
617 | static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) | ||
618 | { | ||
619 | return 0x00000009; | ||
620 | } | ||
621 | static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) | ||
622 | { | ||
623 | return 0x00000015; | ||
624 | } | ||
625 | static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) | ||
626 | { | ||
627 | return 0x00000016; | ||
628 | } | ||
629 | static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) | ||
630 | { | ||
631 | return 0x00000025; | ||
632 | } | ||
633 | static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) | ||
634 | { | ||
635 | return 0x00000030; | ||
636 | } | ||
637 | static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) | ||
638 | { | ||
639 | return 0x00000031; | ||
640 | } | ||
641 | static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) | ||
642 | { | ||
643 | return 0x00000032; | ||
644 | } | ||
645 | static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) | ||
646 | { | ||
647 | return 0x00000038; | ||
648 | } | ||
649 | static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) | ||
650 | { | ||
651 | return 0x00000039; | ||
652 | } | ||
653 | static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | ||
654 | { | ||
655 | return 0x21; | ||
656 | } | ||
657 | static inline u32 gr_fecs_host_int_enable_r(void) | ||
658 | { | ||
659 | return 0x00409c24; | ||
660 | } | ||
661 | static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) | ||
662 | { | ||
663 | return 0x10000; | ||
664 | } | ||
665 | static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) | ||
666 | { | ||
667 | return 0x20000; | ||
668 | } | ||
669 | static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) | ||
670 | { | ||
671 | return 0x40000; | ||
672 | } | ||
673 | static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) | ||
674 | { | ||
675 | return 0x80000; | ||
676 | } | ||
677 | static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) | ||
678 | { | ||
679 | return 0x00409614; | ||
680 | } | ||
681 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) | ||
682 | { | ||
683 | return 0x0; | ||
684 | } | ||
685 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) | ||
686 | { | ||
687 | return 0x0; | ||
688 | } | ||
689 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) | ||
690 | { | ||
691 | return 0x0; | ||
692 | } | ||
693 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) | ||
694 | { | ||
695 | return 0x10; | ||
696 | } | ||
697 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) | ||
698 | { | ||
699 | return 0x20; | ||
700 | } | ||
701 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) | ||
702 | { | ||
703 | return 0x40; | ||
704 | } | ||
705 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) | ||
706 | { | ||
707 | return 0x0; | ||
708 | } | ||
709 | static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) | ||
710 | { | ||
711 | return 0x100; | ||
712 | } | ||
713 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) | ||
714 | { | ||
715 | return 0x0; | ||
716 | } | ||
717 | static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) | ||
718 | { | ||
719 | return 0x200; | ||
720 | } | ||
721 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) | ||
722 | { | ||
723 | return 1; | ||
724 | } | ||
725 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) | ||
726 | { | ||
727 | return (v & 0x1) << 10; | ||
728 | } | ||
729 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) | ||
730 | { | ||
731 | return 0x1 << 10; | ||
732 | } | ||
733 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) | ||
734 | { | ||
735 | return (r >> 10) & 0x1; | ||
736 | } | ||
737 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) | ||
738 | { | ||
739 | return 0x0; | ||
740 | } | ||
741 | static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) | ||
742 | { | ||
743 | return 0x400; | ||
744 | } | ||
745 | static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) | ||
746 | { | ||
747 | return 0x0040960c; | ||
748 | } | ||
749 | static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) | ||
750 | { | ||
751 | return 0x00409800 + i*4; | ||
752 | } | ||
753 | static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) | ||
754 | { | ||
755 | return 0x00000010; | ||
756 | } | ||
757 | static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) | ||
758 | { | ||
759 | return (v & 0xffffffff) << 0; | ||
760 | } | ||
761 | static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) | ||
762 | { | ||
763 | return 0x00000001; | ||
764 | } | ||
765 | static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) | ||
766 | { | ||
767 | return 0x00000002; | ||
768 | } | ||
769 | static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) | ||
770 | { | ||
771 | return 0x004098c0 + i*4; | ||
772 | } | ||
773 | static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) | ||
774 | { | ||
775 | return (v & 0xffffffff) << 0; | ||
776 | } | ||
777 | static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) | ||
778 | { | ||
779 | return 0x00409840 + i*4; | ||
780 | } | ||
781 | static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) | ||
782 | { | ||
783 | return (v & 0xffffffff) << 0; | ||
784 | } | ||
785 | static inline u32 gr_fecs_fs_r(void) | ||
786 | { | ||
787 | return 0x00409604; | ||
788 | } | ||
789 | static inline u32 gr_fecs_fs_num_available_gpcs_s(void) | ||
790 | { | ||
791 | return 5; | ||
792 | } | ||
793 | static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) | ||
794 | { | ||
795 | return (v & 0x1f) << 0; | ||
796 | } | ||
797 | static inline u32 gr_fecs_fs_num_available_gpcs_m(void) | ||
798 | { | ||
799 | return 0x1f << 0; | ||
800 | } | ||
801 | static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) | ||
802 | { | ||
803 | return (r >> 0) & 0x1f; | ||
804 | } | ||
805 | static inline u32 gr_fecs_fs_num_available_fbps_s(void) | ||
806 | { | ||
807 | return 5; | ||
808 | } | ||
809 | static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) | ||
810 | { | ||
811 | return (v & 0x1f) << 16; | ||
812 | } | ||
813 | static inline u32 gr_fecs_fs_num_available_fbps_m(void) | ||
814 | { | ||
815 | return 0x1f << 16; | ||
816 | } | ||
817 | static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) | ||
818 | { | ||
819 | return (r >> 16) & 0x1f; | ||
820 | } | ||
821 | static inline u32 gr_fecs_cfg_r(void) | ||
822 | { | ||
823 | return 0x00409620; | ||
824 | } | ||
825 | static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) | ||
826 | { | ||
827 | return (r >> 0) & 0xff; | ||
828 | } | ||
829 | static inline u32 gr_fecs_rc_lanes_r(void) | ||
830 | { | ||
831 | return 0x00409880; | ||
832 | } | ||
833 | static inline u32 gr_fecs_rc_lanes_num_chains_s(void) | ||
834 | { | ||
835 | return 6; | ||
836 | } | ||
837 | static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) | ||
838 | { | ||
839 | return (v & 0x3f) << 0; | ||
840 | } | ||
841 | static inline u32 gr_fecs_rc_lanes_num_chains_m(void) | ||
842 | { | ||
843 | return 0x3f << 0; | ||
844 | } | ||
845 | static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) | ||
846 | { | ||
847 | return (r >> 0) & 0x3f; | ||
848 | } | ||
849 | static inline u32 gr_fecs_ctxsw_status_1_r(void) | ||
850 | { | ||
851 | return 0x00409400; | ||
852 | } | ||
853 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) | ||
854 | { | ||
855 | return 1; | ||
856 | } | ||
857 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) | ||
858 | { | ||
859 | return (v & 0x1) << 12; | ||
860 | } | ||
861 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) | ||
862 | { | ||
863 | return 0x1 << 12; | ||
864 | } | ||
865 | static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) | ||
866 | { | ||
867 | return (r >> 12) & 0x1; | ||
868 | } | ||
869 | static inline u32 gr_fecs_arb_ctx_adr_r(void) | ||
870 | { | ||
871 | return 0x00409a24; | ||
872 | } | ||
873 | static inline u32 gr_fecs_new_ctx_r(void) | ||
874 | { | ||
875 | return 0x00409b04; | ||
876 | } | ||
877 | static inline u32 gr_fecs_new_ctx_ptr_s(void) | ||
878 | { | ||
879 | return 28; | ||
880 | } | ||
881 | static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) | ||
882 | { | ||
883 | return (v & 0xfffffff) << 0; | ||
884 | } | ||
885 | static inline u32 gr_fecs_new_ctx_ptr_m(void) | ||
886 | { | ||
887 | return 0xfffffff << 0; | ||
888 | } | ||
889 | static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) | ||
890 | { | ||
891 | return (r >> 0) & 0xfffffff; | ||
892 | } | ||
893 | static inline u32 gr_fecs_new_ctx_target_s(void) | ||
894 | { | ||
895 | return 2; | ||
896 | } | ||
897 | static inline u32 gr_fecs_new_ctx_target_f(u32 v) | ||
898 | { | ||
899 | return (v & 0x3) << 28; | ||
900 | } | ||
901 | static inline u32 gr_fecs_new_ctx_target_m(void) | ||
902 | { | ||
903 | return 0x3 << 28; | ||
904 | } | ||
905 | static inline u32 gr_fecs_new_ctx_target_v(u32 r) | ||
906 | { | ||
907 | return (r >> 28) & 0x3; | ||
908 | } | ||
909 | static inline u32 gr_fecs_new_ctx_valid_s(void) | ||
910 | { | ||
911 | return 1; | ||
912 | } | ||
913 | static inline u32 gr_fecs_new_ctx_valid_f(u32 v) | ||
914 | { | ||
915 | return (v & 0x1) << 31; | ||
916 | } | ||
917 | static inline u32 gr_fecs_new_ctx_valid_m(void) | ||
918 | { | ||
919 | return 0x1 << 31; | ||
920 | } | ||
921 | static inline u32 gr_fecs_new_ctx_valid_v(u32 r) | ||
922 | { | ||
923 | return (r >> 31) & 0x1; | ||
924 | } | ||
925 | static inline u32 gr_fecs_arb_ctx_ptr_r(void) | ||
926 | { | ||
927 | return 0x00409a0c; | ||
928 | } | ||
929 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) | ||
930 | { | ||
931 | return 28; | ||
932 | } | ||
933 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) | ||
934 | { | ||
935 | return (v & 0xfffffff) << 0; | ||
936 | } | ||
937 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) | ||
938 | { | ||
939 | return 0xfffffff << 0; | ||
940 | } | ||
941 | static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) | ||
942 | { | ||
943 | return (r >> 0) & 0xfffffff; | ||
944 | } | ||
945 | static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) | ||
946 | { | ||
947 | return 2; | ||
948 | } | ||
949 | static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) | ||
950 | { | ||
951 | return (v & 0x3) << 28; | ||
952 | } | ||
953 | static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) | ||
954 | { | ||
955 | return 0x3 << 28; | ||
956 | } | ||
957 | static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) | ||
958 | { | ||
959 | return (r >> 28) & 0x3; | ||
960 | } | ||
961 | static inline u32 gr_fecs_arb_ctx_cmd_r(void) | ||
962 | { | ||
963 | return 0x00409a10; | ||
964 | } | ||
965 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) | ||
966 | { | ||
967 | return 5; | ||
968 | } | ||
969 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) | ||
970 | { | ||
971 | return (v & 0x1f) << 0; | ||
972 | } | ||
973 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) | ||
974 | { | ||
975 | return 0x1f << 0; | ||
976 | } | ||
977 | static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) | ||
978 | { | ||
979 | return (r >> 0) & 0x1f; | ||
980 | } | ||
981 | static inline u32 gr_rstr2d_gpc_map0_r(void) | ||
982 | { | ||
983 | return 0x0040780c; | ||
984 | } | ||
985 | static inline u32 gr_rstr2d_gpc_map1_r(void) | ||
986 | { | ||
987 | return 0x00407810; | ||
988 | } | ||
989 | static inline u32 gr_rstr2d_gpc_map2_r(void) | ||
990 | { | ||
991 | return 0x00407814; | ||
992 | } | ||
993 | static inline u32 gr_rstr2d_gpc_map3_r(void) | ||
994 | { | ||
995 | return 0x00407818; | ||
996 | } | ||
997 | static inline u32 gr_rstr2d_gpc_map4_r(void) | ||
998 | { | ||
999 | return 0x0040781c; | ||
1000 | } | ||
1001 | static inline u32 gr_rstr2d_gpc_map5_r(void) | ||
1002 | { | ||
1003 | return 0x00407820; | ||
1004 | } | ||
1005 | static inline u32 gr_rstr2d_map_table_cfg_r(void) | ||
1006 | { | ||
1007 | return 0x004078bc; | ||
1008 | } | ||
1009 | static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) | ||
1010 | { | ||
1011 | return (v & 0xff) << 0; | ||
1012 | } | ||
1013 | static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) | ||
1014 | { | ||
1015 | return (v & 0xff) << 8; | ||
1016 | } | ||
1017 | static inline u32 gr_pd_hww_esr_r(void) | ||
1018 | { | ||
1019 | return 0x00406018; | ||
1020 | } | ||
1021 | static inline u32 gr_pd_hww_esr_reset_active_f(void) | ||
1022 | { | ||
1023 | return 0x40000000; | ||
1024 | } | ||
1025 | static inline u32 gr_pd_hww_esr_en_enable_f(void) | ||
1026 | { | ||
1027 | return 0x80000000; | ||
1028 | } | ||
1029 | static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) | ||
1030 | { | ||
1031 | return 0x00406028 + i*4; | ||
1032 | } | ||
1033 | static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) | ||
1034 | { | ||
1035 | return 0x00000004; | ||
1036 | } | ||
1037 | static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) | ||
1038 | { | ||
1039 | return (v & 0xf) << 0; | ||
1040 | } | ||
1041 | static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) | ||
1042 | { | ||
1043 | return (v & 0xf) << 4; | ||
1044 | } | ||
1045 | static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) | ||
1046 | { | ||
1047 | return (v & 0xf) << 8; | ||
1048 | } | ||
1049 | static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) | ||
1050 | { | ||
1051 | return (v & 0xf) << 12; | ||
1052 | } | ||
1053 | static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) | ||
1054 | { | ||
1055 | return (v & 0xf) << 16; | ||
1056 | } | ||
1057 | static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) | ||
1058 | { | ||
1059 | return (v & 0xf) << 20; | ||
1060 | } | ||
1061 | static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) | ||
1062 | { | ||
1063 | return (v & 0xf) << 24; | ||
1064 | } | ||
1065 | static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) | ||
1066 | { | ||
1067 | return (v & 0xf) << 28; | ||
1068 | } | ||
1069 | static inline u32 gr_pd_ab_dist_cfg0_r(void) | ||
1070 | { | ||
1071 | return 0x004064c0; | ||
1072 | } | ||
1073 | static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) | ||
1074 | { | ||
1075 | return 0x80000000; | ||
1076 | } | ||
1077 | static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) | ||
1078 | { | ||
1079 | return 0x0; | ||
1080 | } | ||
1081 | static inline u32 gr_pd_ab_dist_cfg1_r(void) | ||
1082 | { | ||
1083 | return 0x004064c4; | ||
1084 | } | ||
1085 | static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) | ||
1086 | { | ||
1087 | return 0xffff; | ||
1088 | } | ||
1089 | static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) | ||
1090 | { | ||
1091 | return (v & 0xffff) << 16; | ||
1092 | } | ||
1093 | static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) | ||
1094 | { | ||
1095 | return 0x00000080; | ||
1096 | } | ||
1097 | static inline u32 gr_pd_ab_dist_cfg2_r(void) | ||
1098 | { | ||
1099 | return 0x004064c8; | ||
1100 | } | ||
1101 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) | ||
1102 | { | ||
1103 | return (v & 0xfff) << 0; | ||
1104 | } | ||
1105 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) | ||
1106 | { | ||
1107 | return 0x000001c0; | ||
1108 | } | ||
1109 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) | ||
1110 | { | ||
1111 | return (v & 0xfff) << 16; | ||
1112 | } | ||
1113 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) | ||
1114 | { | ||
1115 | return 0x00000020; | ||
1116 | } | ||
1117 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) | ||
1118 | { | ||
1119 | return 0x00000182; | ||
1120 | } | ||
1121 | static inline u32 gr_pd_pagepool_r(void) | ||
1122 | { | ||
1123 | return 0x004064cc; | ||
1124 | } | ||
1125 | static inline u32 gr_pd_pagepool_total_pages_f(u32 v) | ||
1126 | { | ||
1127 | return (v & 0xff) << 0; | ||
1128 | } | ||
1129 | static inline u32 gr_pd_pagepool_valid_true_f(void) | ||
1130 | { | ||
1131 | return 0x80000000; | ||
1132 | } | ||
1133 | static inline u32 gr_pd_dist_skip_table_r(u32 i) | ||
1134 | { | ||
1135 | return 0x004064d0 + i*4; | ||
1136 | } | ||
1137 | static inline u32 gr_pd_dist_skip_table__size_1_v(void) | ||
1138 | { | ||
1139 | return 0x00000008; | ||
1140 | } | ||
1141 | static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) | ||
1142 | { | ||
1143 | return (v & 0xff) << 0; | ||
1144 | } | ||
1145 | static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) | ||
1146 | { | ||
1147 | return (v & 0xff) << 8; | ||
1148 | } | ||
1149 | static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) | ||
1150 | { | ||
1151 | return (v & 0xff) << 16; | ||
1152 | } | ||
1153 | static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) | ||
1154 | { | ||
1155 | return (v & 0xff) << 24; | ||
1156 | } | ||
1157 | static inline u32 gr_ds_debug_r(void) | ||
1158 | { | ||
1159 | return 0x00405800; | ||
1160 | } | ||
1161 | static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) | ||
1162 | { | ||
1163 | return 0x0; | ||
1164 | } | ||
1165 | static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) | ||
1166 | { | ||
1167 | return 0x8000000; | ||
1168 | } | ||
1169 | static inline u32 gr_ds_zbc_color_r_r(void) | ||
1170 | { | ||
1171 | return 0x00405804; | ||
1172 | } | ||
1173 | static inline u32 gr_ds_zbc_color_r_val_f(u32 v) | ||
1174 | { | ||
1175 | return (v & 0xffffffff) << 0; | ||
1176 | } | ||
1177 | static inline u32 gr_ds_zbc_color_g_r(void) | ||
1178 | { | ||
1179 | return 0x00405808; | ||
1180 | } | ||
1181 | static inline u32 gr_ds_zbc_color_g_val_f(u32 v) | ||
1182 | { | ||
1183 | return (v & 0xffffffff) << 0; | ||
1184 | } | ||
1185 | static inline u32 gr_ds_zbc_color_b_r(void) | ||
1186 | { | ||
1187 | return 0x0040580c; | ||
1188 | } | ||
1189 | static inline u32 gr_ds_zbc_color_b_val_f(u32 v) | ||
1190 | { | ||
1191 | return (v & 0xffffffff) << 0; | ||
1192 | } | ||
1193 | static inline u32 gr_ds_zbc_color_a_r(void) | ||
1194 | { | ||
1195 | return 0x00405810; | ||
1196 | } | ||
1197 | static inline u32 gr_ds_zbc_color_a_val_f(u32 v) | ||
1198 | { | ||
1199 | return (v & 0xffffffff) << 0; | ||
1200 | } | ||
1201 | static inline u32 gr_ds_zbc_color_fmt_r(void) | ||
1202 | { | ||
1203 | return 0x00405814; | ||
1204 | } | ||
1205 | static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) | ||
1206 | { | ||
1207 | return (v & 0x7f) << 0; | ||
1208 | } | ||
1209 | static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) | ||
1210 | { | ||
1211 | return 0x0; | ||
1212 | } | ||
1213 | static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) | ||
1214 | { | ||
1215 | return 0x00000001; | ||
1216 | } | ||
1217 | static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) | ||
1218 | { | ||
1219 | return 0x00000002; | ||
1220 | } | ||
1221 | static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) | ||
1222 | { | ||
1223 | return 0x00000004; | ||
1224 | } | ||
1225 | static inline u32 gr_ds_zbc_z_r(void) | ||
1226 | { | ||
1227 | return 0x00405818; | ||
1228 | } | ||
1229 | static inline u32 gr_ds_zbc_z_val_s(void) | ||
1230 | { | ||
1231 | return 32; | ||
1232 | } | ||
1233 | static inline u32 gr_ds_zbc_z_val_f(u32 v) | ||
1234 | { | ||
1235 | return (v & 0xffffffff) << 0; | ||
1236 | } | ||
1237 | static inline u32 gr_ds_zbc_z_val_m(void) | ||
1238 | { | ||
1239 | return 0xffffffff << 0; | ||
1240 | } | ||
1241 | static inline u32 gr_ds_zbc_z_val_v(u32 r) | ||
1242 | { | ||
1243 | return (r >> 0) & 0xffffffff; | ||
1244 | } | ||
1245 | static inline u32 gr_ds_zbc_z_val__init_v(void) | ||
1246 | { | ||
1247 | return 0x00000000; | ||
1248 | } | ||
1249 | static inline u32 gr_ds_zbc_z_val__init_f(void) | ||
1250 | { | ||
1251 | return 0x0; | ||
1252 | } | ||
1253 | static inline u32 gr_ds_zbc_z_fmt_r(void) | ||
1254 | { | ||
1255 | return 0x0040581c; | ||
1256 | } | ||
1257 | static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) | ||
1258 | { | ||
1259 | return (v & 0x1) << 0; | ||
1260 | } | ||
1261 | static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) | ||
1262 | { | ||
1263 | return 0x0; | ||
1264 | } | ||
1265 | static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) | ||
1266 | { | ||
1267 | return 0x00000001; | ||
1268 | } | ||
1269 | static inline u32 gr_ds_zbc_tbl_index_r(void) | ||
1270 | { | ||
1271 | return 0x00405820; | ||
1272 | } | ||
1273 | static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) | ||
1274 | { | ||
1275 | return (v & 0xf) << 0; | ||
1276 | } | ||
1277 | static inline u32 gr_ds_zbc_tbl_ld_r(void) | ||
1278 | { | ||
1279 | return 0x00405824; | ||
1280 | } | ||
1281 | static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) | ||
1282 | { | ||
1283 | return 0x0; | ||
1284 | } | ||
1285 | static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) | ||
1286 | { | ||
1287 | return 0x1; | ||
1288 | } | ||
1289 | static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) | ||
1290 | { | ||
1291 | return 0x0; | ||
1292 | } | ||
1293 | static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) | ||
1294 | { | ||
1295 | return 0x4; | ||
1296 | } | ||
1297 | static inline u32 gr_ds_tga_constraintlogic_r(void) | ||
1298 | { | ||
1299 | return 0x00405830; | ||
1300 | } | ||
1301 | static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) | ||
1302 | { | ||
1303 | return (v & 0xffff) << 16; | ||
1304 | } | ||
1305 | static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) | ||
1306 | { | ||
1307 | return (v & 0xffff) << 0; | ||
1308 | } | ||
1309 | static inline u32 gr_ds_hww_esr_r(void) | ||
1310 | { | ||
1311 | return 0x00405840; | ||
1312 | } | ||
1313 | static inline u32 gr_ds_hww_esr_reset_s(void) | ||
1314 | { | ||
1315 | return 1; | ||
1316 | } | ||
1317 | static inline u32 gr_ds_hww_esr_reset_f(u32 v) | ||
1318 | { | ||
1319 | return (v & 0x1) << 30; | ||
1320 | } | ||
1321 | static inline u32 gr_ds_hww_esr_reset_m(void) | ||
1322 | { | ||
1323 | return 0x1 << 30; | ||
1324 | } | ||
1325 | static inline u32 gr_ds_hww_esr_reset_v(u32 r) | ||
1326 | { | ||
1327 | return (r >> 30) & 0x1; | ||
1328 | } | ||
1329 | static inline u32 gr_ds_hww_esr_reset_task_v(void) | ||
1330 | { | ||
1331 | return 0x00000001; | ||
1332 | } | ||
1333 | static inline u32 gr_ds_hww_esr_reset_task_f(void) | ||
1334 | { | ||
1335 | return 0x40000000; | ||
1336 | } | ||
1337 | static inline u32 gr_ds_hww_esr_en_enabled_f(void) | ||
1338 | { | ||
1339 | return 0x80000000; | ||
1340 | } | ||
1341 | static inline u32 gr_ds_hww_esr_2_r(void) | ||
1342 | { | ||
1343 | return 0x00405848; | ||
1344 | } | ||
1345 | static inline u32 gr_ds_hww_esr_2_reset_s(void) | ||
1346 | { | ||
1347 | return 1; | ||
1348 | } | ||
1349 | static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) | ||
1350 | { | ||
1351 | return (v & 0x1) << 30; | ||
1352 | } | ||
1353 | static inline u32 gr_ds_hww_esr_2_reset_m(void) | ||
1354 | { | ||
1355 | return 0x1 << 30; | ||
1356 | } | ||
1357 | static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) | ||
1358 | { | ||
1359 | return (r >> 30) & 0x1; | ||
1360 | } | ||
1361 | static inline u32 gr_ds_hww_esr_2_reset_task_v(void) | ||
1362 | { | ||
1363 | return 0x00000001; | ||
1364 | } | ||
1365 | static inline u32 gr_ds_hww_esr_2_reset_task_f(void) | ||
1366 | { | ||
1367 | return 0x40000000; | ||
1368 | } | ||
1369 | static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) | ||
1370 | { | ||
1371 | return 0x80000000; | ||
1372 | } | ||
1373 | static inline u32 gr_ds_hww_report_mask_r(void) | ||
1374 | { | ||
1375 | return 0x00405844; | ||
1376 | } | ||
1377 | static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) | ||
1378 | { | ||
1379 | return 0x1; | ||
1380 | } | ||
1381 | static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) | ||
1382 | { | ||
1383 | return 0x2; | ||
1384 | } | ||
1385 | static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) | ||
1386 | { | ||
1387 | return 0x4; | ||
1388 | } | ||
1389 | static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) | ||
1390 | { | ||
1391 | return 0x8; | ||
1392 | } | ||
1393 | static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) | ||
1394 | { | ||
1395 | return 0x10; | ||
1396 | } | ||
1397 | static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) | ||
1398 | { | ||
1399 | return 0x20; | ||
1400 | } | ||
1401 | static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) | ||
1402 | { | ||
1403 | return 0x40; | ||
1404 | } | ||
1405 | static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) | ||
1406 | { | ||
1407 | return 0x80; | ||
1408 | } | ||
1409 | static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) | ||
1410 | { | ||
1411 | return 0x100; | ||
1412 | } | ||
1413 | static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) | ||
1414 | { | ||
1415 | return 0x200; | ||
1416 | } | ||
1417 | static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) | ||
1418 | { | ||
1419 | return 0x400; | ||
1420 | } | ||
1421 | static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) | ||
1422 | { | ||
1423 | return 0x800; | ||
1424 | } | ||
1425 | static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) | ||
1426 | { | ||
1427 | return 0x1000; | ||
1428 | } | ||
1429 | static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) | ||
1430 | { | ||
1431 | return 0x2000; | ||
1432 | } | ||
1433 | static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) | ||
1434 | { | ||
1435 | return 0x4000; | ||
1436 | } | ||
1437 | static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) | ||
1438 | { | ||
1439 | return 0x8000; | ||
1440 | } | ||
1441 | static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) | ||
1442 | { | ||
1443 | return 0x10000; | ||
1444 | } | ||
1445 | static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) | ||
1446 | { | ||
1447 | return 0x20000; | ||
1448 | } | ||
1449 | static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) | ||
1450 | { | ||
1451 | return 0x40000; | ||
1452 | } | ||
1453 | static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) | ||
1454 | { | ||
1455 | return 0x80000; | ||
1456 | } | ||
1457 | static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) | ||
1458 | { | ||
1459 | return 0x100000; | ||
1460 | } | ||
1461 | static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) | ||
1462 | { | ||
1463 | return 0x200000; | ||
1464 | } | ||
1465 | static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) | ||
1466 | { | ||
1467 | return 0x400000; | ||
1468 | } | ||
1469 | static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) | ||
1470 | { | ||
1471 | return 0x800000; | ||
1472 | } | ||
1473 | static inline u32 gr_ds_hww_report_mask_2_r(void) | ||
1474 | { | ||
1475 | return 0x0040584c; | ||
1476 | } | ||
1477 | static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) | ||
1478 | { | ||
1479 | return 0x1; | ||
1480 | } | ||
1481 | static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) | ||
1482 | { | ||
1483 | return 0x00405870 + i*4; | ||
1484 | } | ||
1485 | static inline u32 gr_scc_bundle_cb_base_r(void) | ||
1486 | { | ||
1487 | return 0x00408004; | ||
1488 | } | ||
1489 | static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) | ||
1490 | { | ||
1491 | return (v & 0xffffffff) << 0; | ||
1492 | } | ||
1493 | static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) | ||
1494 | { | ||
1495 | return 0x00000008; | ||
1496 | } | ||
1497 | static inline u32 gr_scc_bundle_cb_size_r(void) | ||
1498 | { | ||
1499 | return 0x00408008; | ||
1500 | } | ||
1501 | static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) | ||
1502 | { | ||
1503 | return (v & 0x7ff) << 0; | ||
1504 | } | ||
1505 | static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) | ||
1506 | { | ||
1507 | return 0x00000018; | ||
1508 | } | ||
1509 | static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) | ||
1510 | { | ||
1511 | return 0x00000100; | ||
1512 | } | ||
1513 | static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) | ||
1514 | { | ||
1515 | return 0x00000000; | ||
1516 | } | ||
1517 | static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) | ||
1518 | { | ||
1519 | return 0x0; | ||
1520 | } | ||
1521 | static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) | ||
1522 | { | ||
1523 | return 0x80000000; | ||
1524 | } | ||
1525 | static inline u32 gr_scc_pagepool_base_r(void) | ||
1526 | { | ||
1527 | return 0x0040800c; | ||
1528 | } | ||
1529 | static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) | ||
1530 | { | ||
1531 | return (v & 0xffffffff) << 0; | ||
1532 | } | ||
1533 | static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) | ||
1534 | { | ||
1535 | return 0x00000008; | ||
1536 | } | ||
1537 | static inline u32 gr_scc_pagepool_r(void) | ||
1538 | { | ||
1539 | return 0x00408010; | ||
1540 | } | ||
1541 | static inline u32 gr_scc_pagepool_total_pages_f(u32 v) | ||
1542 | { | ||
1543 | return (v & 0xff) << 0; | ||
1544 | } | ||
1545 | static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) | ||
1546 | { | ||
1547 | return 0x00000000; | ||
1548 | } | ||
1549 | static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) | ||
1550 | { | ||
1551 | return 0x00000080; | ||
1552 | } | ||
1553 | static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) | ||
1554 | { | ||
1555 | return 0x00000100; | ||
1556 | } | ||
1557 | static inline u32 gr_scc_pagepool_max_valid_pages_s(void) | ||
1558 | { | ||
1559 | return 8; | ||
1560 | } | ||
1561 | static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) | ||
1562 | { | ||
1563 | return (v & 0xff) << 8; | ||
1564 | } | ||
1565 | static inline u32 gr_scc_pagepool_max_valid_pages_m(void) | ||
1566 | { | ||
1567 | return 0xff << 8; | ||
1568 | } | ||
1569 | static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) | ||
1570 | { | ||
1571 | return (r >> 8) & 0xff; | ||
1572 | } | ||
1573 | static inline u32 gr_scc_pagepool_valid_true_f(void) | ||
1574 | { | ||
1575 | return 0x80000000; | ||
1576 | } | ||
1577 | static inline u32 gr_scc_init_r(void) | ||
1578 | { | ||
1579 | return 0x0040802c; | ||
1580 | } | ||
1581 | static inline u32 gr_scc_init_ram_trigger_f(void) | ||
1582 | { | ||
1583 | return 0x1; | ||
1584 | } | ||
1585 | static inline u32 gr_scc_hww_esr_r(void) | ||
1586 | { | ||
1587 | return 0x00408030; | ||
1588 | } | ||
1589 | static inline u32 gr_scc_hww_esr_reset_active_f(void) | ||
1590 | { | ||
1591 | return 0x40000000; | ||
1592 | } | ||
1593 | static inline u32 gr_scc_hww_esr_en_enable_f(void) | ||
1594 | { | ||
1595 | return 0x80000000; | ||
1596 | } | ||
1597 | static inline u32 gr_sked_hww_esr_r(void) | ||
1598 | { | ||
1599 | return 0x00407020; | ||
1600 | } | ||
1601 | static inline u32 gr_sked_hww_esr_reset_active_f(void) | ||
1602 | { | ||
1603 | return 0x40000000; | ||
1604 | } | ||
1605 | static inline u32 gr_cwd_fs_r(void) | ||
1606 | { | ||
1607 | return 0x00405b00; | ||
1608 | } | ||
1609 | static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) | ||
1610 | { | ||
1611 | return (v & 0xff) << 0; | ||
1612 | } | ||
1613 | static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) | ||
1614 | { | ||
1615 | return (v & 0xff) << 8; | ||
1616 | } | ||
1617 | static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) | ||
1618 | { | ||
1619 | return 0x00405b60 + i*4; | ||
1620 | } | ||
1621 | static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) | ||
1622 | { | ||
1623 | return (v & 0xf) << 0; | ||
1624 | } | ||
1625 | static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) | ||
1626 | { | ||
1627 | return (v & 0xf) << 8; | ||
1628 | } | ||
1629 | static inline u32 gr_cwd_sm_id_r(u32 i) | ||
1630 | { | ||
1631 | return 0x00405ba0 + i*4; | ||
1632 | } | ||
1633 | static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) | ||
1634 | { | ||
1635 | return (v & 0xff) << 0; | ||
1636 | } | ||
1637 | static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) | ||
1638 | { | ||
1639 | return (v & 0xff) << 8; | ||
1640 | } | ||
1641 | static inline u32 gr_gpc0_fs_gpc_r(void) | ||
1642 | { | ||
1643 | return 0x00502608; | ||
1644 | } | ||
1645 | static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) | ||
1646 | { | ||
1647 | return (r >> 0) & 0x1f; | ||
1648 | } | ||
1649 | static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) | ||
1650 | { | ||
1651 | return (r >> 16) & 0x1f; | ||
1652 | } | ||
1653 | static inline u32 gr_gpc0_cfg_r(void) | ||
1654 | { | ||
1655 | return 0x00502620; | ||
1656 | } | ||
1657 | static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) | ||
1658 | { | ||
1659 | return (r >> 0) & 0xff; | ||
1660 | } | ||
1661 | static inline u32 gr_gpccs_rc_lanes_r(void) | ||
1662 | { | ||
1663 | return 0x00502880; | ||
1664 | } | ||
1665 | static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) | ||
1666 | { | ||
1667 | return 6; | ||
1668 | } | ||
1669 | static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) | ||
1670 | { | ||
1671 | return (v & 0x3f) << 0; | ||
1672 | } | ||
1673 | static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) | ||
1674 | { | ||
1675 | return 0x3f << 0; | ||
1676 | } | ||
1677 | static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) | ||
1678 | { | ||
1679 | return (r >> 0) & 0x3f; | ||
1680 | } | ||
1681 | static inline u32 gr_gpccs_rc_lane_size_r(u32 i) | ||
1682 | { | ||
1683 | return 0x00502910 + i*0; | ||
1684 | } | ||
1685 | static inline u32 gr_gpccs_rc_lane_size__size_1_v(void) | ||
1686 | { | ||
1687 | return 0x00000010; | ||
1688 | } | ||
1689 | static inline u32 gr_gpccs_rc_lane_size_v_s(void) | ||
1690 | { | ||
1691 | return 24; | ||
1692 | } | ||
1693 | static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) | ||
1694 | { | ||
1695 | return (v & 0xffffff) << 0; | ||
1696 | } | ||
1697 | static inline u32 gr_gpccs_rc_lane_size_v_m(void) | ||
1698 | { | ||
1699 | return 0xffffff << 0; | ||
1700 | } | ||
1701 | static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) | ||
1702 | { | ||
1703 | return (r >> 0) & 0xffffff; | ||
1704 | } | ||
1705 | static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) | ||
1706 | { | ||
1707 | return 0x00000000; | ||
1708 | } | ||
1709 | static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) | ||
1710 | { | ||
1711 | return 0x0; | ||
1712 | } | ||
1713 | static inline u32 gr_gpc0_zcull_fs_r(void) | ||
1714 | { | ||
1715 | return 0x00500910; | ||
1716 | } | ||
1717 | static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) | ||
1718 | { | ||
1719 | return (v & 0x1ff) << 0; | ||
1720 | } | ||
1721 | static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) | ||
1722 | { | ||
1723 | return (v & 0xf) << 16; | ||
1724 | } | ||
1725 | static inline u32 gr_gpc0_zcull_ram_addr_r(void) | ||
1726 | { | ||
1727 | return 0x00500914; | ||
1728 | } | ||
1729 | static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) | ||
1730 | { | ||
1731 | return (v & 0xf) << 0; | ||
1732 | } | ||
1733 | static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) | ||
1734 | { | ||
1735 | return (v & 0xf) << 8; | ||
1736 | } | ||
1737 | static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) | ||
1738 | { | ||
1739 | return 0x00500918; | ||
1740 | } | ||
1741 | static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) | ||
1742 | { | ||
1743 | return (v & 0xffffff) << 0; | ||
1744 | } | ||
1745 | static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) | ||
1746 | { | ||
1747 | return 0x00800000; | ||
1748 | } | ||
1749 | static inline u32 gr_gpc0_zcull_total_ram_size_r(void) | ||
1750 | { | ||
1751 | return 0x00500920; | ||
1752 | } | ||
1753 | static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) | ||
1754 | { | ||
1755 | return (v & 0xffff) << 0; | ||
1756 | } | ||
1757 | static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) | ||
1758 | { | ||
1759 | return 0x00500a04 + i*32; | ||
1760 | } | ||
1761 | static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) | ||
1762 | { | ||
1763 | return 0x00000040; | ||
1764 | } | ||
1765 | static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) | ||
1766 | { | ||
1767 | return 0x00000010; | ||
1768 | } | ||
1769 | static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) | ||
1770 | { | ||
1771 | return 0x00500c10 + i*4; | ||
1772 | } | ||
1773 | static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) | ||
1774 | { | ||
1775 | return (v & 0xff) << 0; | ||
1776 | } | ||
1777 | static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) | ||
1778 | { | ||
1779 | return 0x00500c30 + i*4; | ||
1780 | } | ||
1781 | static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) | ||
1782 | { | ||
1783 | return (r >> 0) & 0xff; | ||
1784 | } | ||
1785 | static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) | ||
1786 | { | ||
1787 | return 0x00504088; | ||
1788 | } | ||
1789 | static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) | ||
1790 | { | ||
1791 | return (v & 0xffff) << 0; | ||
1792 | } | ||
1793 | static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) | ||
1794 | { | ||
1795 | return 0x00504698; | ||
1796 | } | ||
1797 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) | ||
1798 | { | ||
1799 | return (v & 0xffff) << 0; | ||
1800 | } | ||
1801 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) | ||
1802 | { | ||
1803 | return 0x00503018; | ||
1804 | } | ||
1805 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) | ||
1806 | { | ||
1807 | return 0x1 << 0; | ||
1808 | } | ||
1809 | static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) | ||
1810 | { | ||
1811 | return 0x1; | ||
1812 | } | ||
1813 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) | ||
1814 | { | ||
1815 | return 0x005030c0; | ||
1816 | } | ||
1817 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) | ||
1818 | { | ||
1819 | return (v & 0xffff) << 0; | ||
1820 | } | ||
1821 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) | ||
1822 | { | ||
1823 | return 0xffff << 0; | ||
1824 | } | ||
1825 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) | ||
1826 | { | ||
1827 | return 0x00000400; | ||
1828 | } | ||
1829 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) | ||
1830 | { | ||
1831 | return 0x00000020; | ||
1832 | } | ||
1833 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) | ||
1834 | { | ||
1835 | return 0x005030f4; | ||
1836 | } | ||
1837 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) | ||
1838 | { | ||
1839 | return 0x005030e4; | ||
1840 | } | ||
1841 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) | ||
1842 | { | ||
1843 | return (v & 0xffff) << 0; | ||
1844 | } | ||
1845 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) | ||
1846 | { | ||
1847 | return 0xffff << 0; | ||
1848 | } | ||
1849 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) | ||
1850 | { | ||
1851 | return 0x00000800; | ||
1852 | } | ||
1853 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) | ||
1854 | { | ||
1855 | return 0x00000020; | ||
1856 | } | ||
1857 | static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) | ||
1858 | { | ||
1859 | return 0x005030f8; | ||
1860 | } | ||
1861 | static inline u32 gr_gpccs_falcon_addr_r(void) | ||
1862 | { | ||
1863 | return 0x0041a0ac; | ||
1864 | } | ||
1865 | static inline u32 gr_gpccs_falcon_addr_lsb_s(void) | ||
1866 | { | ||
1867 | return 6; | ||
1868 | } | ||
1869 | static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) | ||
1870 | { | ||
1871 | return (v & 0x3f) << 0; | ||
1872 | } | ||
1873 | static inline u32 gr_gpccs_falcon_addr_lsb_m(void) | ||
1874 | { | ||
1875 | return 0x3f << 0; | ||
1876 | } | ||
1877 | static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) | ||
1878 | { | ||
1879 | return (r >> 0) & 0x3f; | ||
1880 | } | ||
1881 | static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) | ||
1882 | { | ||
1883 | return 0x00000000; | ||
1884 | } | ||
1885 | static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) | ||
1886 | { | ||
1887 | return 0x0; | ||
1888 | } | ||
1889 | static inline u32 gr_gpccs_falcon_addr_msb_s(void) | ||
1890 | { | ||
1891 | return 6; | ||
1892 | } | ||
1893 | static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) | ||
1894 | { | ||
1895 | return (v & 0x3f) << 6; | ||
1896 | } | ||
1897 | static inline u32 gr_gpccs_falcon_addr_msb_m(void) | ||
1898 | { | ||
1899 | return 0x3f << 6; | ||
1900 | } | ||
1901 | static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) | ||
1902 | { | ||
1903 | return (r >> 6) & 0x3f; | ||
1904 | } | ||
1905 | static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) | ||
1906 | { | ||
1907 | return 0x00000000; | ||
1908 | } | ||
1909 | static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) | ||
1910 | { | ||
1911 | return 0x0; | ||
1912 | } | ||
1913 | static inline u32 gr_gpccs_falcon_addr_ext_s(void) | ||
1914 | { | ||
1915 | return 12; | ||
1916 | } | ||
1917 | static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) | ||
1918 | { | ||
1919 | return (v & 0xfff) << 0; | ||
1920 | } | ||
1921 | static inline u32 gr_gpccs_falcon_addr_ext_m(void) | ||
1922 | { | ||
1923 | return 0xfff << 0; | ||
1924 | } | ||
1925 | static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) | ||
1926 | { | ||
1927 | return (r >> 0) & 0xfff; | ||
1928 | } | ||
1929 | static inline u32 gr_gpccs_cpuctl_r(void) | ||
1930 | { | ||
1931 | return 0x0041a100; | ||
1932 | } | ||
1933 | static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) | ||
1934 | { | ||
1935 | return (v & 0x1) << 1; | ||
1936 | } | ||
1937 | static inline u32 gr_gpccs_dmactl_r(void) | ||
1938 | { | ||
1939 | return 0x0041a10c; | ||
1940 | } | ||
1941 | static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) | ||
1942 | { | ||
1943 | return (v & 0x1) << 0; | ||
1944 | } | ||
1945 | static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) | ||
1946 | { | ||
1947 | return 0x1 << 1; | ||
1948 | } | ||
1949 | static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) | ||
1950 | { | ||
1951 | return 0x1 << 2; | ||
1952 | } | ||
1953 | static inline u32 gr_gpccs_imemc_r(u32 i) | ||
1954 | { | ||
1955 | return 0x0041a180 + i*16; | ||
1956 | } | ||
1957 | static inline u32 gr_gpccs_imemc_offs_f(u32 v) | ||
1958 | { | ||
1959 | return (v & 0x3f) << 2; | ||
1960 | } | ||
1961 | static inline u32 gr_gpccs_imemc_blk_f(u32 v) | ||
1962 | { | ||
1963 | return (v & 0xff) << 8; | ||
1964 | } | ||
1965 | static inline u32 gr_gpccs_imemc_aincw_f(u32 v) | ||
1966 | { | ||
1967 | return (v & 0x1) << 24; | ||
1968 | } | ||
1969 | static inline u32 gr_gpccs_imemd_r(u32 i) | ||
1970 | { | ||
1971 | return 0x0041a184 + i*16; | ||
1972 | } | ||
1973 | static inline u32 gr_gpccs_imemt_r(u32 i) | ||
1974 | { | ||
1975 | return 0x0041a188 + i*16; | ||
1976 | } | ||
1977 | static inline u32 gr_gpccs_imemt__size_1_v(void) | ||
1978 | { | ||
1979 | return 0x00000004; | ||
1980 | } | ||
1981 | static inline u32 gr_gpccs_imemt_tag_f(u32 v) | ||
1982 | { | ||
1983 | return (v & 0xffff) << 0; | ||
1984 | } | ||
1985 | static inline u32 gr_gpccs_dmemc_r(u32 i) | ||
1986 | { | ||
1987 | return 0x0041a1c0 + i*8; | ||
1988 | } | ||
1989 | static inline u32 gr_gpccs_dmemc_offs_f(u32 v) | ||
1990 | { | ||
1991 | return (v & 0x3f) << 2; | ||
1992 | } | ||
1993 | static inline u32 gr_gpccs_dmemc_blk_f(u32 v) | ||
1994 | { | ||
1995 | return (v & 0xff) << 8; | ||
1996 | } | ||
1997 | static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) | ||
1998 | { | ||
1999 | return (v & 0x1) << 24; | ||
2000 | } | ||
2001 | static inline u32 gr_gpccs_dmemd_r(u32 i) | ||
2002 | { | ||
2003 | return 0x0041a1c4 + i*8; | ||
2004 | } | ||
2005 | static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) | ||
2006 | { | ||
2007 | return 0x0041a800 + i*4; | ||
2008 | } | ||
2009 | static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) | ||
2010 | { | ||
2011 | return (v & 0xffffffff) << 0; | ||
2012 | } | ||
2013 | static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) | ||
2014 | { | ||
2015 | return 0x00418e24; | ||
2016 | } | ||
2017 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) | ||
2018 | { | ||
2019 | return 32; | ||
2020 | } | ||
2021 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) | ||
2022 | { | ||
2023 | return (v & 0xffffffff) << 0; | ||
2024 | } | ||
2025 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) | ||
2026 | { | ||
2027 | return 0xffffffff << 0; | ||
2028 | } | ||
2029 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) | ||
2030 | { | ||
2031 | return (r >> 0) & 0xffffffff; | ||
2032 | } | ||
2033 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) | ||
2034 | { | ||
2035 | return 0x00000000; | ||
2036 | } | ||
2037 | static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) | ||
2038 | { | ||
2039 | return 0x0; | ||
2040 | } | ||
2041 | static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) | ||
2042 | { | ||
2043 | return 0x00418e28; | ||
2044 | } | ||
2045 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) | ||
2046 | { | ||
2047 | return 11; | ||
2048 | } | ||
2049 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) | ||
2050 | { | ||
2051 | return (v & 0x7ff) << 0; | ||
2052 | } | ||
2053 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) | ||
2054 | { | ||
2055 | return 0x7ff << 0; | ||
2056 | } | ||
2057 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) | ||
2058 | { | ||
2059 | return (r >> 0) & 0x7ff; | ||
2060 | } | ||
2061 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) | ||
2062 | { | ||
2063 | return 0x00000018; | ||
2064 | } | ||
2065 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) | ||
2066 | { | ||
2067 | return 0x18; | ||
2068 | } | ||
2069 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) | ||
2070 | { | ||
2071 | return 1; | ||
2072 | } | ||
2073 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) | ||
2074 | { | ||
2075 | return (v & 0x1) << 31; | ||
2076 | } | ||
2077 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) | ||
2078 | { | ||
2079 | return 0x1 << 31; | ||
2080 | } | ||
2081 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) | ||
2082 | { | ||
2083 | return (r >> 31) & 0x1; | ||
2084 | } | ||
2085 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) | ||
2086 | { | ||
2087 | return 0x00000000; | ||
2088 | } | ||
2089 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) | ||
2090 | { | ||
2091 | return 0x0; | ||
2092 | } | ||
2093 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) | ||
2094 | { | ||
2095 | return 0x00000001; | ||
2096 | } | ||
2097 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) | ||
2098 | { | ||
2099 | return 0x80000000; | ||
2100 | } | ||
2101 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) | ||
2102 | { | ||
2103 | return 0x00418ea0 + i*4; | ||
2104 | } | ||
2105 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) | ||
2106 | { | ||
2107 | return (v & 0xffff) << 0; | ||
2108 | } | ||
2109 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) | ||
2110 | { | ||
2111 | return 0xffff << 0; | ||
2112 | } | ||
2113 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) | ||
2114 | { | ||
2115 | return (v & 0xffff) << 16; | ||
2116 | } | ||
2117 | static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) | ||
2118 | { | ||
2119 | return 0xffff << 16; | ||
2120 | } | ||
2121 | static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) | ||
2122 | { | ||
2123 | return 0x00418e30; | ||
2124 | } | ||
2125 | static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v) | ||
2126 | { | ||
2127 | return (v & 0xff) << 0; | ||
2128 | } | ||
2129 | static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void) | ||
2130 | { | ||
2131 | return 0x80000000; | ||
2132 | } | ||
2133 | static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) | ||
2134 | { | ||
2135 | return 0x00418810; | ||
2136 | } | ||
2137 | static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) | ||
2138 | { | ||
2139 | return (v & 0xfffffff) << 0; | ||
2140 | } | ||
2141 | static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) | ||
2142 | { | ||
2143 | return 0x0000000c; | ||
2144 | } | ||
2145 | static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) | ||
2146 | { | ||
2147 | return 0x80000000; | ||
2148 | } | ||
2149 | static inline u32 gr_crstr_gpc_map0_r(void) | ||
2150 | { | ||
2151 | return 0x00418b08; | ||
2152 | } | ||
2153 | static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) | ||
2154 | { | ||
2155 | return (v & 0x7) << 0; | ||
2156 | } | ||
2157 | static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) | ||
2158 | { | ||
2159 | return (v & 0x7) << 5; | ||
2160 | } | ||
2161 | static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) | ||
2162 | { | ||
2163 | return (v & 0x7) << 10; | ||
2164 | } | ||
2165 | static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) | ||
2166 | { | ||
2167 | return (v & 0x7) << 15; | ||
2168 | } | ||
2169 | static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) | ||
2170 | { | ||
2171 | return (v & 0x7) << 20; | ||
2172 | } | ||
2173 | static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) | ||
2174 | { | ||
2175 | return (v & 0x7) << 25; | ||
2176 | } | ||
2177 | static inline u32 gr_crstr_gpc_map1_r(void) | ||
2178 | { | ||
2179 | return 0x00418b0c; | ||
2180 | } | ||
2181 | static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) | ||
2182 | { | ||
2183 | return (v & 0x7) << 0; | ||
2184 | } | ||
2185 | static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) | ||
2186 | { | ||
2187 | return (v & 0x7) << 5; | ||
2188 | } | ||
2189 | static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) | ||
2190 | { | ||
2191 | return (v & 0x7) << 10; | ||
2192 | } | ||
2193 | static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) | ||
2194 | { | ||
2195 | return (v & 0x7) << 15; | ||
2196 | } | ||
2197 | static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) | ||
2198 | { | ||
2199 | return (v & 0x7) << 20; | ||
2200 | } | ||
2201 | static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) | ||
2202 | { | ||
2203 | return (v & 0x7) << 25; | ||
2204 | } | ||
2205 | static inline u32 gr_crstr_gpc_map2_r(void) | ||
2206 | { | ||
2207 | return 0x00418b10; | ||
2208 | } | ||
2209 | static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) | ||
2210 | { | ||
2211 | return (v & 0x7) << 0; | ||
2212 | } | ||
2213 | static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) | ||
2214 | { | ||
2215 | return (v & 0x7) << 5; | ||
2216 | } | ||
2217 | static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) | ||
2218 | { | ||
2219 | return (v & 0x7) << 10; | ||
2220 | } | ||
2221 | static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) | ||
2222 | { | ||
2223 | return (v & 0x7) << 15; | ||
2224 | } | ||
2225 | static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) | ||
2226 | { | ||
2227 | return (v & 0x7) << 20; | ||
2228 | } | ||
2229 | static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) | ||
2230 | { | ||
2231 | return (v & 0x7) << 25; | ||
2232 | } | ||
2233 | static inline u32 gr_crstr_gpc_map3_r(void) | ||
2234 | { | ||
2235 | return 0x00418b14; | ||
2236 | } | ||
2237 | static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) | ||
2238 | { | ||
2239 | return (v & 0x7) << 0; | ||
2240 | } | ||
2241 | static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) | ||
2242 | { | ||
2243 | return (v & 0x7) << 5; | ||
2244 | } | ||
2245 | static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) | ||
2246 | { | ||
2247 | return (v & 0x7) << 10; | ||
2248 | } | ||
2249 | static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) | ||
2250 | { | ||
2251 | return (v & 0x7) << 15; | ||
2252 | } | ||
2253 | static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) | ||
2254 | { | ||
2255 | return (v & 0x7) << 20; | ||
2256 | } | ||
2257 | static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) | ||
2258 | { | ||
2259 | return (v & 0x7) << 25; | ||
2260 | } | ||
2261 | static inline u32 gr_crstr_gpc_map4_r(void) | ||
2262 | { | ||
2263 | return 0x00418b18; | ||
2264 | } | ||
2265 | static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) | ||
2266 | { | ||
2267 | return (v & 0x7) << 0; | ||
2268 | } | ||
2269 | static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) | ||
2270 | { | ||
2271 | return (v & 0x7) << 5; | ||
2272 | } | ||
2273 | static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) | ||
2274 | { | ||
2275 | return (v & 0x7) << 10; | ||
2276 | } | ||
2277 | static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) | ||
2278 | { | ||
2279 | return (v & 0x7) << 15; | ||
2280 | } | ||
2281 | static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) | ||
2282 | { | ||
2283 | return (v & 0x7) << 20; | ||
2284 | } | ||
2285 | static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) | ||
2286 | { | ||
2287 | return (v & 0x7) << 25; | ||
2288 | } | ||
2289 | static inline u32 gr_crstr_gpc_map5_r(void) | ||
2290 | { | ||
2291 | return 0x00418b1c; | ||
2292 | } | ||
2293 | static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) | ||
2294 | { | ||
2295 | return (v & 0x7) << 0; | ||
2296 | } | ||
2297 | static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) | ||
2298 | { | ||
2299 | return (v & 0x7) << 5; | ||
2300 | } | ||
2301 | static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) | ||
2302 | { | ||
2303 | return (v & 0x7) << 10; | ||
2304 | } | ||
2305 | static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) | ||
2306 | { | ||
2307 | return (v & 0x7) << 15; | ||
2308 | } | ||
2309 | static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) | ||
2310 | { | ||
2311 | return (v & 0x7) << 20; | ||
2312 | } | ||
2313 | static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) | ||
2314 | { | ||
2315 | return (v & 0x7) << 25; | ||
2316 | } | ||
2317 | static inline u32 gr_crstr_map_table_cfg_r(void) | ||
2318 | { | ||
2319 | return 0x00418bb8; | ||
2320 | } | ||
2321 | static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) | ||
2322 | { | ||
2323 | return (v & 0xff) << 0; | ||
2324 | } | ||
2325 | static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) | ||
2326 | { | ||
2327 | return (v & 0xff) << 8; | ||
2328 | } | ||
2329 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) | ||
2330 | { | ||
2331 | return 0x00418980; | ||
2332 | } | ||
2333 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) | ||
2334 | { | ||
2335 | return (v & 0x7) << 0; | ||
2336 | } | ||
2337 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) | ||
2338 | { | ||
2339 | return (v & 0x7) << 4; | ||
2340 | } | ||
2341 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) | ||
2342 | { | ||
2343 | return (v & 0x7) << 8; | ||
2344 | } | ||
2345 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) | ||
2346 | { | ||
2347 | return (v & 0x7) << 12; | ||
2348 | } | ||
2349 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) | ||
2350 | { | ||
2351 | return (v & 0x7) << 16; | ||
2352 | } | ||
2353 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) | ||
2354 | { | ||
2355 | return (v & 0x7) << 20; | ||
2356 | } | ||
2357 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) | ||
2358 | { | ||
2359 | return (v & 0x7) << 24; | ||
2360 | } | ||
2361 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) | ||
2362 | { | ||
2363 | return (v & 0x7) << 28; | ||
2364 | } | ||
2365 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) | ||
2366 | { | ||
2367 | return 0x00418984; | ||
2368 | } | ||
2369 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) | ||
2370 | { | ||
2371 | return (v & 0x7) << 0; | ||
2372 | } | ||
2373 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) | ||
2374 | { | ||
2375 | return (v & 0x7) << 4; | ||
2376 | } | ||
2377 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) | ||
2378 | { | ||
2379 | return (v & 0x7) << 8; | ||
2380 | } | ||
2381 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) | ||
2382 | { | ||
2383 | return (v & 0x7) << 12; | ||
2384 | } | ||
2385 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) | ||
2386 | { | ||
2387 | return (v & 0x7) << 16; | ||
2388 | } | ||
2389 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) | ||
2390 | { | ||
2391 | return (v & 0x7) << 20; | ||
2392 | } | ||
2393 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) | ||
2394 | { | ||
2395 | return (v & 0x7) << 24; | ||
2396 | } | ||
2397 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) | ||
2398 | { | ||
2399 | return (v & 0x7) << 28; | ||
2400 | } | ||
2401 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) | ||
2402 | { | ||
2403 | return 0x00418988; | ||
2404 | } | ||
2405 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) | ||
2406 | { | ||
2407 | return (v & 0x7) << 0; | ||
2408 | } | ||
2409 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) | ||
2410 | { | ||
2411 | return (v & 0x7) << 4; | ||
2412 | } | ||
2413 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) | ||
2414 | { | ||
2415 | return (v & 0x7) << 8; | ||
2416 | } | ||
2417 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) | ||
2418 | { | ||
2419 | return (v & 0x7) << 12; | ||
2420 | } | ||
2421 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) | ||
2422 | { | ||
2423 | return (v & 0x7) << 16; | ||
2424 | } | ||
2425 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) | ||
2426 | { | ||
2427 | return (v & 0x7) << 20; | ||
2428 | } | ||
2429 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) | ||
2430 | { | ||
2431 | return (v & 0x7) << 24; | ||
2432 | } | ||
2433 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) | ||
2434 | { | ||
2435 | return 3; | ||
2436 | } | ||
2437 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) | ||
2438 | { | ||
2439 | return (v & 0x7) << 28; | ||
2440 | } | ||
2441 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) | ||
2442 | { | ||
2443 | return 0x7 << 28; | ||
2444 | } | ||
2445 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) | ||
2446 | { | ||
2447 | return (r >> 28) & 0x7; | ||
2448 | } | ||
2449 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) | ||
2450 | { | ||
2451 | return 0x0041898c; | ||
2452 | } | ||
2453 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) | ||
2454 | { | ||
2455 | return (v & 0x7) << 0; | ||
2456 | } | ||
2457 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) | ||
2458 | { | ||
2459 | return (v & 0x7) << 4; | ||
2460 | } | ||
2461 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) | ||
2462 | { | ||
2463 | return (v & 0x7) << 8; | ||
2464 | } | ||
2465 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) | ||
2466 | { | ||
2467 | return (v & 0x7) << 12; | ||
2468 | } | ||
2469 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) | ||
2470 | { | ||
2471 | return (v & 0x7) << 16; | ||
2472 | } | ||
2473 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) | ||
2474 | { | ||
2475 | return (v & 0x7) << 20; | ||
2476 | } | ||
2477 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) | ||
2478 | { | ||
2479 | return (v & 0x7) << 24; | ||
2480 | } | ||
2481 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) | ||
2482 | { | ||
2483 | return (v & 0x7) << 28; | ||
2484 | } | ||
2485 | static inline u32 gr_gpcs_gpm_pd_cfg_r(void) | ||
2486 | { | ||
2487 | return 0x00418c6c; | ||
2488 | } | ||
2489 | static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) | ||
2490 | { | ||
2491 | return 0x0; | ||
2492 | } | ||
2493 | static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) | ||
2494 | { | ||
2495 | return 0x1; | ||
2496 | } | ||
2497 | static inline u32 gr_gpcs_gcc_pagepool_base_r(void) | ||
2498 | { | ||
2499 | return 0x00419004; | ||
2500 | } | ||
2501 | static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) | ||
2502 | { | ||
2503 | return (v & 0xffffffff) << 0; | ||
2504 | } | ||
2505 | static inline u32 gr_gpcs_gcc_pagepool_r(void) | ||
2506 | { | ||
2507 | return 0x00419008; | ||
2508 | } | ||
2509 | static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) | ||
2510 | { | ||
2511 | return (v & 0xff) << 0; | ||
2512 | } | ||
2513 | static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) | ||
2514 | { | ||
2515 | return 0x0041980c; | ||
2516 | } | ||
2517 | static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) | ||
2518 | { | ||
2519 | return 0x10; | ||
2520 | } | ||
2521 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) | ||
2522 | { | ||
2523 | return 0x00419848; | ||
2524 | } | ||
2525 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) | ||
2526 | { | ||
2527 | return (v & 0xfffffff) << 0; | ||
2528 | } | ||
2529 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) | ||
2530 | { | ||
2531 | return (v & 0x1) << 28; | ||
2532 | } | ||
2533 | static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) | ||
2534 | { | ||
2535 | return 0x10000000; | ||
2536 | } | ||
2537 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) | ||
2538 | { | ||
2539 | return 0x00419c00; | ||
2540 | } | ||
2541 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) | ||
2542 | { | ||
2543 | return 0x0; | ||
2544 | } | ||
2545 | static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) | ||
2546 | { | ||
2547 | return 0x8; | ||
2548 | } | ||
2549 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) | ||
2550 | { | ||
2551 | return 0x00419c2c; | ||
2552 | } | ||
2553 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) | ||
2554 | { | ||
2555 | return (v & 0xfffffff) << 0; | ||
2556 | } | ||
2557 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) | ||
2558 | { | ||
2559 | return (v & 0x1) << 28; | ||
2560 | } | ||
2561 | static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | ||
2562 | { | ||
2563 | return 0x10000000; | ||
2564 | } | ||
2565 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) | ||
2566 | { | ||
2567 | return 0x00419e00; | ||
2568 | } | ||
2569 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) | ||
2570 | { | ||
2571 | return 0x1 << 7; | ||
2572 | } | ||
2573 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) | ||
2574 | { | ||
2575 | return 0x80; | ||
2576 | } | ||
2577 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) | ||
2578 | { | ||
2579 | return 0x1 << 15; | ||
2580 | } | ||
2581 | static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) | ||
2582 | { | ||
2583 | return 0x8000; | ||
2584 | } | ||
2585 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) | ||
2586 | { | ||
2587 | return 0x00419e44; | ||
2588 | } | ||
2589 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) | ||
2590 | { | ||
2591 | return 0x2; | ||
2592 | } | ||
2593 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) | ||
2594 | { | ||
2595 | return 0x4; | ||
2596 | } | ||
2597 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) | ||
2598 | { | ||
2599 | return 0x8; | ||
2600 | } | ||
2601 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) | ||
2602 | { | ||
2603 | return 0x10; | ||
2604 | } | ||
2605 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) | ||
2606 | { | ||
2607 | return 0x20; | ||
2608 | } | ||
2609 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) | ||
2610 | { | ||
2611 | return 0x40; | ||
2612 | } | ||
2613 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) | ||
2614 | { | ||
2615 | return 0x80; | ||
2616 | } | ||
2617 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) | ||
2618 | { | ||
2619 | return 0x100; | ||
2620 | } | ||
2621 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) | ||
2622 | { | ||
2623 | return 0x200; | ||
2624 | } | ||
2625 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) | ||
2626 | { | ||
2627 | return 0x400; | ||
2628 | } | ||
2629 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) | ||
2630 | { | ||
2631 | return 0x800; | ||
2632 | } | ||
2633 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) | ||
2634 | { | ||
2635 | return 0x1000; | ||
2636 | } | ||
2637 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) | ||
2638 | { | ||
2639 | return 0x2000; | ||
2640 | } | ||
2641 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) | ||
2642 | { | ||
2643 | return 0x4000; | ||
2644 | } | ||
2645 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) | ||
2646 | { | ||
2647 | return 0x8000; | ||
2648 | } | ||
2649 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) | ||
2650 | { | ||
2651 | return 0x10000; | ||
2652 | } | ||
2653 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) | ||
2654 | { | ||
2655 | return 0x20000; | ||
2656 | } | ||
2657 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) | ||
2658 | { | ||
2659 | return 0x40000; | ||
2660 | } | ||
2661 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) | ||
2662 | { | ||
2663 | return 0x800000; | ||
2664 | } | ||
2665 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) | ||
2666 | { | ||
2667 | return 0x400000; | ||
2668 | } | ||
2669 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) | ||
2670 | { | ||
2671 | return 0x80000; | ||
2672 | } | ||
2673 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) | ||
2674 | { | ||
2675 | return 0x100000; | ||
2676 | } | ||
2677 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) | ||
2678 | { | ||
2679 | return 0x00419e4c; | ||
2680 | } | ||
2681 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) | ||
2682 | { | ||
2683 | return 0x1; | ||
2684 | } | ||
2685 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) | ||
2686 | { | ||
2687 | return 0x2; | ||
2688 | } | ||
2689 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) | ||
2690 | { | ||
2691 | return 0x4; | ||
2692 | } | ||
2693 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) | ||
2694 | { | ||
2695 | return 0x8; | ||
2696 | } | ||
2697 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) | ||
2698 | { | ||
2699 | return 0x10; | ||
2700 | } | ||
2701 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) | ||
2702 | { | ||
2703 | return 0x20; | ||
2704 | } | ||
2705 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) | ||
2706 | { | ||
2707 | return 0x40; | ||
2708 | } | ||
2709 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | ||
2710 | { | ||
2711 | return 0x0050450c; | ||
2712 | } | ||
2713 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | ||
2714 | { | ||
2715 | return 0x2; | ||
2716 | } | ||
2717 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void) | ||
2718 | { | ||
2719 | return 0x0; | ||
2720 | } | ||
2721 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void) | ||
2722 | { | ||
2723 | return 0x00502c94; | ||
2724 | } | ||
2725 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void) | ||
2726 | { | ||
2727 | return 0x10000; | ||
2728 | } | ||
2729 | static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void) | ||
2730 | { | ||
2731 | return 0x0; | ||
2732 | } | ||
2733 | static inline u32 gr_gpcs_gpccs_gpc_exception_r(void) | ||
2734 | { | ||
2735 | return 0x0041ac90; | ||
2736 | } | ||
2737 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r) | ||
2738 | { | ||
2739 | return (r >> 16) & 0xff; | ||
2740 | } | ||
2741 | static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void) | ||
2742 | { | ||
2743 | return 0x00000001; | ||
2744 | } | ||
2745 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void) | ||
2746 | { | ||
2747 | return 0x00419d08; | ||
2748 | } | ||
2749 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r) | ||
2750 | { | ||
2751 | return (r >> 1) & 0x1; | ||
2752 | } | ||
2753 | static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void) | ||
2754 | { | ||
2755 | return 0x00000001; | ||
2756 | } | ||
2757 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) | ||
2758 | { | ||
2759 | return 0x00504610; | ||
2760 | } | ||
2761 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) | ||
2762 | { | ||
2763 | return (r >> 0) & 0x1; | ||
2764 | } | ||
2765 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) | ||
2766 | { | ||
2767 | return 0x00000001; | ||
2768 | } | ||
2769 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | ||
2770 | { | ||
2771 | return 0x80000000; | ||
2772 | } | ||
2773 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | ||
2774 | { | ||
2775 | return 0x0050460c; | ||
2776 | } | ||
2777 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) | ||
2778 | { | ||
2779 | return (r >> 4) & 0x1; | ||
2780 | } | ||
2781 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) | ||
2782 | { | ||
2783 | return 0x00000001; | ||
2784 | } | ||
2785 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | ||
2786 | { | ||
2787 | return 0x00504650; | ||
2788 | } | ||
2789 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) | ||
2790 | { | ||
2791 | return 0x10; | ||
2792 | } | ||
2793 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) | ||
2794 | { | ||
2795 | return 0x20; | ||
2796 | } | ||
2797 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) | ||
2798 | { | ||
2799 | return 0x40; | ||
2800 | } | ||
2801 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) | ||
2802 | { | ||
2803 | return 0x00504648; | ||
2804 | } | ||
2805 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) | ||
2806 | { | ||
2807 | return (r >> 0) & 0xffff; | ||
2808 | } | ||
2809 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) | ||
2810 | { | ||
2811 | return 0x00000000; | ||
2812 | } | ||
2813 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) | ||
2814 | { | ||
2815 | return 0x0; | ||
2816 | } | ||
2817 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | ||
2818 | { | ||
2819 | return 0x00504770; | ||
2820 | } | ||
2821 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) | ||
2822 | { | ||
2823 | return 0x00419f70; | ||
2824 | } | ||
2825 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) | ||
2826 | { | ||
2827 | return 0x1 << 4; | ||
2828 | } | ||
2829 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) | ||
2830 | { | ||
2831 | return (v & 0x1) << 4; | ||
2832 | } | ||
2833 | static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) | ||
2834 | { | ||
2835 | return 0x0050477c; | ||
2836 | } | ||
2837 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) | ||
2838 | { | ||
2839 | return 0x00419f7c; | ||
2840 | } | ||
2841 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) | ||
2842 | { | ||
2843 | return 0x1 << 0; | ||
2844 | } | ||
2845 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) | ||
2846 | { | ||
2847 | return (v & 0x1) << 0; | ||
2848 | } | ||
2849 | static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) | ||
2850 | { | ||
2851 | return 0x00419ed8; | ||
2852 | } | ||
2853 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) | ||
2854 | { | ||
2855 | return 0x0041be08; | ||
2856 | } | ||
2857 | static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) | ||
2858 | { | ||
2859 | return 0x4; | ||
2860 | } | ||
2861 | static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) | ||
2862 | { | ||
2863 | return 0x0041bf00; | ||
2864 | } | ||
2865 | static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) | ||
2866 | { | ||
2867 | return 0x0041bf04; | ||
2868 | } | ||
2869 | static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) | ||
2870 | { | ||
2871 | return 0x0041bf08; | ||
2872 | } | ||
2873 | static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) | ||
2874 | { | ||
2875 | return 0x0041bf0c; | ||
2876 | } | ||
2877 | static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) | ||
2878 | { | ||
2879 | return 0x0041bf10; | ||
2880 | } | ||
2881 | static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) | ||
2882 | { | ||
2883 | return 0x0041bf14; | ||
2884 | } | ||
2885 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) | ||
2886 | { | ||
2887 | return 0x0041bfd0; | ||
2888 | } | ||
2889 | static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) | ||
2890 | { | ||
2891 | return (v & 0xff) << 0; | ||
2892 | } | ||
2893 | static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) | ||
2894 | { | ||
2895 | return (v & 0xff) << 8; | ||
2896 | } | ||
2897 | static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) | ||
2898 | { | ||
2899 | return (v & 0x1f) << 16; | ||
2900 | } | ||
2901 | static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) | ||
2902 | { | ||
2903 | return (v & 0x7) << 21; | ||
2904 | } | ||
2905 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) | ||
2906 | { | ||
2907 | return (v & 0x1f) << 24; | ||
2908 | } | ||
2909 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) | ||
2910 | { | ||
2911 | return 0x0041bfd4; | ||
2912 | } | ||
2913 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) | ||
2914 | { | ||
2915 | return (v & 0xffffff) << 0; | ||
2916 | } | ||
2917 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) | ||
2918 | { | ||
2919 | return 0x0041bfe4; | ||
2920 | } | ||
2921 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) | ||
2922 | { | ||
2923 | return (v & 0x1f) << 0; | ||
2924 | } | ||
2925 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) | ||
2926 | { | ||
2927 | return (v & 0x1f) << 5; | ||
2928 | } | ||
2929 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) | ||
2930 | { | ||
2931 | return (v & 0x1f) << 10; | ||
2932 | } | ||
2933 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) | ||
2934 | { | ||
2935 | return (v & 0x1f) << 15; | ||
2936 | } | ||
2937 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) | ||
2938 | { | ||
2939 | return (v & 0x1f) << 20; | ||
2940 | } | ||
2941 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) | ||
2942 | { | ||
2943 | return (v & 0x1f) << 25; | ||
2944 | } | ||
2945 | static inline u32 gr_bes_zrop_settings_r(void) | ||
2946 | { | ||
2947 | return 0x00408850; | ||
2948 | } | ||
2949 | static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) | ||
2950 | { | ||
2951 | return (v & 0xf) << 0; | ||
2952 | } | ||
2953 | static inline u32 gr_be0_crop_debug3_r(void) | ||
2954 | { | ||
2955 | return 0x00410108; | ||
2956 | } | ||
2957 | static inline u32 gr_bes_crop_debug3_r(void) | ||
2958 | { | ||
2959 | return 0x00408908; | ||
2960 | } | ||
2961 | static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) | ||
2962 | { | ||
2963 | return 0x1 << 31; | ||
2964 | } | ||
2965 | static inline u32 gr_bes_crop_settings_r(void) | ||
2966 | { | ||
2967 | return 0x00408958; | ||
2968 | } | ||
2969 | static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) | ||
2970 | { | ||
2971 | return (v & 0xf) << 0; | ||
2972 | } | ||
2973 | static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) | ||
2974 | { | ||
2975 | return 0x00000020; | ||
2976 | } | ||
2977 | static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) | ||
2978 | { | ||
2979 | return 0x00000020; | ||
2980 | } | ||
2981 | static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) | ||
2982 | { | ||
2983 | return 0x000000c0; | ||
2984 | } | ||
2985 | static inline u32 gr_zcull_subregion_qty_v(void) | ||
2986 | { | ||
2987 | return 0x00000010; | ||
2988 | } | ||
2989 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) | ||
2990 | { | ||
2991 | return 0x00504604; | ||
2992 | } | ||
2993 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) | ||
2994 | { | ||
2995 | return 0x00504608; | ||
2996 | } | ||
2997 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) | ||
2998 | { | ||
2999 | return 0x0050465c; | ||
3000 | } | ||
3001 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) | ||
3002 | { | ||
3003 | return 0x00504660; | ||
3004 | } | ||
3005 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) | ||
3006 | { | ||
3007 | return 0x00504664; | ||
3008 | } | ||
3009 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) | ||
3010 | { | ||
3011 | return 0x00504668; | ||
3012 | } | ||
3013 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) | ||
3014 | { | ||
3015 | return 0x0050466c; | ||
3016 | } | ||
3017 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) | ||
3018 | { | ||
3019 | return 0x00504658; | ||
3020 | } | ||
3021 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) | ||
3022 | { | ||
3023 | return 0x00504730; | ||
3024 | } | ||
3025 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) | ||
3026 | { | ||
3027 | return 0x00504734; | ||
3028 | } | ||
3029 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) | ||
3030 | { | ||
3031 | return 0x00504738; | ||
3032 | } | ||
3033 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) | ||
3034 | { | ||
3035 | return 0x0050473c; | ||
3036 | } | ||
3037 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) | ||
3038 | { | ||
3039 | return 0x00504740; | ||
3040 | } | ||
3041 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) | ||
3042 | { | ||
3043 | return 0x00504744; | ||
3044 | } | ||
3045 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) | ||
3046 | { | ||
3047 | return 0x00504748; | ||
3048 | } | ||
3049 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) | ||
3050 | { | ||
3051 | return 0x0050474c; | ||
3052 | } | ||
3053 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) | ||
3054 | { | ||
3055 | return 0x00504678; | ||
3056 | } | ||
3057 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) | ||
3058 | { | ||
3059 | return 0x00504694; | ||
3060 | } | ||
3061 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) | ||
3062 | { | ||
3063 | return 0x005046f0; | ||
3064 | } | ||
3065 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) | ||
3066 | { | ||
3067 | return 0x00504700; | ||
3068 | } | ||
3069 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) | ||
3070 | { | ||
3071 | return 0x005046f4; | ||
3072 | } | ||
3073 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) | ||
3074 | { | ||
3075 | return 0x00504704; | ||
3076 | } | ||
3077 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) | ||
3078 | { | ||
3079 | return 0x005046f8; | ||
3080 | } | ||
3081 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) | ||
3082 | { | ||
3083 | return 0x00504708; | ||
3084 | } | ||
3085 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) | ||
3086 | { | ||
3087 | return 0x005046fc; | ||
3088 | } | ||
3089 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) | ||
3090 | { | ||
3091 | return 0x0050470c; | ||
3092 | } | ||
3093 | static inline u32 gr_fe_pwr_mode_r(void) | ||
3094 | { | ||
3095 | return 0x00404170; | ||
3096 | } | ||
3097 | static inline u32 gr_fe_pwr_mode_mode_auto_f(void) | ||
3098 | { | ||
3099 | return 0x0; | ||
3100 | } | ||
3101 | static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) | ||
3102 | { | ||
3103 | return 0x2; | ||
3104 | } | ||
3105 | static inline u32 gr_fe_pwr_mode_req_v(u32 r) | ||
3106 | { | ||
3107 | return (r >> 4) & 0x1; | ||
3108 | } | ||
3109 | static inline u32 gr_fe_pwr_mode_req_send_f(void) | ||
3110 | { | ||
3111 | return 0x10; | ||
3112 | } | ||
3113 | static inline u32 gr_fe_pwr_mode_req_done_v(void) | ||
3114 | { | ||
3115 | return 0x00000000; | ||
3116 | } | ||
3117 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void) | ||
3118 | { | ||
3119 | return 0x00419f88; | ||
3120 | } | ||
3121 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v) | ||
3122 | { | ||
3123 | return (v & 0x1) << 31; | ||
3124 | } | ||
3125 | static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void) | ||
3126 | { | ||
3127 | return 0x1 << 31; | ||
3128 | } | ||
3129 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void) | ||
3130 | { | ||
3131 | return 0x00419f80; | ||
3132 | } | ||
3133 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v) | ||
3134 | { | ||
3135 | return (v & 0x1) << 31; | ||
3136 | } | ||
3137 | static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void) | ||
3138 | { | ||
3139 | return 0x1 << 31; | ||
3140 | } | ||
3141 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void) | ||
3142 | { | ||
3143 | return 0x00419ccc; | ||
3144 | } | ||
3145 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v) | ||
3146 | { | ||
3147 | return (v & 0x1) << 31; | ||
3148 | } | ||
3149 | static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void) | ||
3150 | { | ||
3151 | return 0x1 << 31; | ||
3152 | } | ||
3153 | static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) | ||
3154 | { | ||
3155 | return 0x00418880; | ||
3156 | } | ||
3157 | static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) | ||
3158 | { | ||
3159 | return 0x1 << 0; | ||
3160 | } | ||
3161 | static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) | ||
3162 | { | ||
3163 | return 0x1 << 11; | ||
3164 | } | ||
3165 | static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) | ||
3166 | { | ||
3167 | return 0x1 << 1; | ||
3168 | } | ||
3169 | static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) | ||
3170 | { | ||
3171 | return 0x1 << 2; | ||
3172 | } | ||
3173 | static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) | ||
3174 | { | ||
3175 | return 0x3 << 3; | ||
3176 | } | ||
3177 | static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) | ||
3178 | { | ||
3179 | return 0x3 << 5; | ||
3180 | } | ||
3181 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) | ||
3182 | { | ||
3183 | return 0x3 << 28; | ||
3184 | } | ||
3185 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) | ||
3186 | { | ||
3187 | return 0x1 << 30; | ||
3188 | } | ||
3189 | static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) | ||
3190 | { | ||
3191 | return 0x1 << 31; | ||
3192 | } | ||
3193 | static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) | ||
3194 | { | ||
3195 | return 0x00418890; | ||
3196 | } | ||
3197 | static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) | ||
3198 | { | ||
3199 | return 0x00418894; | ||
3200 | } | ||
3201 | static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) | ||
3202 | { | ||
3203 | return 0x004188b0; | ||
3204 | } | ||
3205 | static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) | ||
3206 | { | ||
3207 | return 0x004188b4; | ||
3208 | } | ||
3209 | static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) | ||
3210 | { | ||
3211 | return 0x004188b8; | ||
3212 | } | ||
3213 | static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | ||
3214 | { | ||
3215 | return 0x004188ac; | ||
3216 | } | ||
3217 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h new file mode 100644 index 00000000..38a3121f --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_ltc_gm20b.h | |||
@@ -0,0 +1,257 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ltc_gm20b_h_ | ||
51 | #define _hw_ltc_gm20b_h_ | ||
52 | |||
53 | static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) | ||
54 | { | ||
55 | return 0x0014046c; | ||
56 | } | ||
57 | static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) | ||
58 | { | ||
59 | return 0x00140518; | ||
60 | } | ||
61 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) | ||
62 | { | ||
63 | return 0x0017e318; | ||
64 | } | ||
65 | static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) | ||
66 | { | ||
67 | return 0x1 << 15; | ||
68 | } | ||
69 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) | ||
70 | { | ||
71 | return 0x00140494; | ||
72 | } | ||
73 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) | ||
74 | { | ||
75 | return (r >> 0) & 0xffff; | ||
76 | } | ||
77 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) | ||
78 | { | ||
79 | return (r >> 16) & 0x3; | ||
80 | } | ||
81 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) | ||
82 | { | ||
83 | return 0x00000000; | ||
84 | } | ||
85 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) | ||
86 | { | ||
87 | return 0x00000001; | ||
88 | } | ||
89 | static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) | ||
90 | { | ||
91 | return 0x00000002; | ||
92 | } | ||
93 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) | ||
94 | { | ||
95 | return 0x0017e26c; | ||
96 | } | ||
97 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) | ||
98 | { | ||
99 | return (r >> 2) & 0x1; | ||
100 | } | ||
101 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) | ||
102 | { | ||
103 | return 0x00000001; | ||
104 | } | ||
105 | static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) | ||
106 | { | ||
107 | return 0x4; | ||
108 | } | ||
109 | static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) | ||
110 | { | ||
111 | return 0x0017e26c; | ||
112 | } | ||
113 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) | ||
114 | { | ||
115 | return 0x0017e270; | ||
116 | } | ||
117 | static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) | ||
118 | { | ||
119 | return (v & 0x1ffff) << 0; | ||
120 | } | ||
121 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) | ||
122 | { | ||
123 | return 0x0017e274; | ||
124 | } | ||
125 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) | ||
126 | { | ||
127 | return (v & 0x1ffff) << 0; | ||
128 | } | ||
129 | static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) | ||
130 | { | ||
131 | return 0x0001ffff; | ||
132 | } | ||
133 | static inline u32 ltc_ltcs_ltss_cbc_base_r(void) | ||
134 | { | ||
135 | return 0x0017e278; | ||
136 | } | ||
137 | static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) | ||
138 | { | ||
139 | return 0x0000000b; | ||
140 | } | ||
141 | static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) | ||
142 | { | ||
143 | return (r >> 0) & 0x3ffffff; | ||
144 | } | ||
145 | static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) | ||
146 | { | ||
147 | return 0x0017e27c; | ||
148 | } | ||
149 | static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) | ||
150 | { | ||
151 | return 0x0017e000; | ||
152 | } | ||
153 | static inline u32 ltc_ltcs_ltss_cbc_param_r(void) | ||
154 | { | ||
155 | return 0x0017e280; | ||
156 | } | ||
157 | static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) | ||
158 | { | ||
159 | return (r >> 0) & 0xffff; | ||
160 | } | ||
161 | static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) | ||
162 | { | ||
163 | return (r >> 24) & 0xf; | ||
164 | } | ||
165 | static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) | ||
166 | { | ||
167 | return (r >> 28) & 0xf; | ||
168 | } | ||
169 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) | ||
170 | { | ||
171 | return 0x0017e2ac; | ||
172 | } | ||
173 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) | ||
174 | { | ||
175 | return (v & 0x1f) << 16; | ||
176 | } | ||
177 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) | ||
178 | { | ||
179 | return 0x0017e338; | ||
180 | } | ||
181 | static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) | ||
182 | { | ||
183 | return (v & 0xf) << 0; | ||
184 | } | ||
185 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) | ||
186 | { | ||
187 | return 0x0017e33c + i*4; | ||
188 | } | ||
189 | static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) | ||
190 | { | ||
191 | return 0x00000004; | ||
192 | } | ||
193 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) | ||
194 | { | ||
195 | return 0x0017e34c; | ||
196 | } | ||
197 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) | ||
198 | { | ||
199 | return 32; | ||
200 | } | ||
201 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) | ||
202 | { | ||
203 | return (v & 0xffffffff) << 0; | ||
204 | } | ||
205 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) | ||
206 | { | ||
207 | return 0xffffffff << 0; | ||
208 | } | ||
209 | static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) | ||
210 | { | ||
211 | return (r >> 0) & 0xffffffff; | ||
212 | } | ||
213 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) | ||
214 | { | ||
215 | return 0x0017e2b0; | ||
216 | } | ||
217 | static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) | ||
218 | { | ||
219 | return 0x10000000; | ||
220 | } | ||
221 | static inline u32 ltc_ltcs_ltss_g_elpg_r(void) | ||
222 | { | ||
223 | return 0x0017e214; | ||
224 | } | ||
225 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) | ||
226 | { | ||
227 | return (r >> 0) & 0x1; | ||
228 | } | ||
229 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) | ||
230 | { | ||
231 | return 0x00000001; | ||
232 | } | ||
233 | static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) | ||
234 | { | ||
235 | return 0x1; | ||
236 | } | ||
237 | static inline u32 ltc_ltc0_ltss_g_elpg_r(void) | ||
238 | { | ||
239 | return 0x00140214; | ||
240 | } | ||
241 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) | ||
242 | { | ||
243 | return (r >> 0) & 0x1; | ||
244 | } | ||
245 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) | ||
246 | { | ||
247 | return 0x00000001; | ||
248 | } | ||
249 | static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) | ||
250 | { | ||
251 | return 0x1; | ||
252 | } | ||
253 | static inline u32 ltc_ltc0_ltss_intr_r(void) | ||
254 | { | ||
255 | return 0x0014020c; | ||
256 | } | ||
257 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h new file mode 100644 index 00000000..e978adf2 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h | |||
@@ -0,0 +1,217 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_mc_gm20b_h_ | ||
51 | #define _hw_mc_gm20b_h_ | ||
52 | |||
53 | static inline u32 mc_intr_0_r(void) | ||
54 | { | ||
55 | return 0x00000100; | ||
56 | } | ||
57 | static inline u32 mc_intr_0_pfifo_pending_f(void) | ||
58 | { | ||
59 | return 0x100; | ||
60 | } | ||
61 | static inline u32 mc_intr_0_pgraph_pending_f(void) | ||
62 | { | ||
63 | return 0x1000; | ||
64 | } | ||
65 | static inline u32 mc_intr_0_pmu_pending_f(void) | ||
66 | { | ||
67 | return 0x1000000; | ||
68 | } | ||
69 | static inline u32 mc_intr_0_ltc_pending_f(void) | ||
70 | { | ||
71 | return 0x2000000; | ||
72 | } | ||
73 | static inline u32 mc_intr_0_priv_ring_pending_f(void) | ||
74 | { | ||
75 | return 0x40000000; | ||
76 | } | ||
77 | static inline u32 mc_intr_0_pbus_pending_f(void) | ||
78 | { | ||
79 | return 0x10000000; | ||
80 | } | ||
81 | static inline u32 mc_intr_mask_0_r(void) | ||
82 | { | ||
83 | return 0x00000640; | ||
84 | } | ||
85 | static inline u32 mc_intr_mask_0_pmu_enabled_f(void) | ||
86 | { | ||
87 | return 0x1000000; | ||
88 | } | ||
89 | static inline u32 mc_intr_en_0_r(void) | ||
90 | { | ||
91 | return 0x00000140; | ||
92 | } | ||
93 | static inline u32 mc_intr_en_0_inta_disabled_f(void) | ||
94 | { | ||
95 | return 0x0; | ||
96 | } | ||
97 | static inline u32 mc_intr_en_0_inta_hardware_f(void) | ||
98 | { | ||
99 | return 0x1; | ||
100 | } | ||
101 | static inline u32 mc_intr_en_1_r(void) | ||
102 | { | ||
103 | return 0x00000144; | ||
104 | } | ||
105 | static inline u32 mc_intr_en_1_inta_disabled_f(void) | ||
106 | { | ||
107 | return 0x0; | ||
108 | } | ||
109 | static inline u32 mc_enable_r(void) | ||
110 | { | ||
111 | return 0x00000200; | ||
112 | } | ||
113 | static inline u32 mc_enable_xbar_enabled_f(void) | ||
114 | { | ||
115 | return 0x4; | ||
116 | } | ||
117 | static inline u32 mc_enable_l2_enabled_f(void) | ||
118 | { | ||
119 | return 0x8; | ||
120 | } | ||
121 | static inline u32 mc_enable_pmedia_s(void) | ||
122 | { | ||
123 | return 1; | ||
124 | } | ||
125 | static inline u32 mc_enable_pmedia_f(u32 v) | ||
126 | { | ||
127 | return (v & 0x1) << 4; | ||
128 | } | ||
129 | static inline u32 mc_enable_pmedia_m(void) | ||
130 | { | ||
131 | return 0x1 << 4; | ||
132 | } | ||
133 | static inline u32 mc_enable_pmedia_v(u32 r) | ||
134 | { | ||
135 | return (r >> 4) & 0x1; | ||
136 | } | ||
137 | static inline u32 mc_enable_priv_ring_enabled_f(void) | ||
138 | { | ||
139 | return 0x20; | ||
140 | } | ||
141 | static inline u32 mc_enable_ce0_m(void) | ||
142 | { | ||
143 | return 0x1 << 6; | ||
144 | } | ||
145 | static inline u32 mc_enable_pfifo_enabled_f(void) | ||
146 | { | ||
147 | return 0x100; | ||
148 | } | ||
149 | static inline u32 mc_enable_pgraph_enabled_f(void) | ||
150 | { | ||
151 | return 0x1000; | ||
152 | } | ||
153 | static inline u32 mc_enable_pwr_v(u32 r) | ||
154 | { | ||
155 | return (r >> 13) & 0x1; | ||
156 | } | ||
157 | static inline u32 mc_enable_pwr_disabled_v(void) | ||
158 | { | ||
159 | return 0x00000000; | ||
160 | } | ||
161 | static inline u32 mc_enable_pwr_enabled_f(void) | ||
162 | { | ||
163 | return 0x2000; | ||
164 | } | ||
165 | static inline u32 mc_enable_pfb_enabled_f(void) | ||
166 | { | ||
167 | return 0x100000; | ||
168 | } | ||
169 | static inline u32 mc_enable_ce2_m(void) | ||
170 | { | ||
171 | return 0x1 << 21; | ||
172 | } | ||
173 | static inline u32 mc_enable_ce2_enabled_f(void) | ||
174 | { | ||
175 | return 0x200000; | ||
176 | } | ||
177 | static inline u32 mc_enable_blg_enabled_f(void) | ||
178 | { | ||
179 | return 0x8000000; | ||
180 | } | ||
181 | static inline u32 mc_enable_perfmon_enabled_f(void) | ||
182 | { | ||
183 | return 0x10000000; | ||
184 | } | ||
185 | static inline u32 mc_enable_hub_enabled_f(void) | ||
186 | { | ||
187 | return 0x20000000; | ||
188 | } | ||
189 | static inline u32 mc_enable_pb_r(void) | ||
190 | { | ||
191 | return 0x00000204; | ||
192 | } | ||
193 | static inline u32 mc_enable_pb_0_s(void) | ||
194 | { | ||
195 | return 1; | ||
196 | } | ||
197 | static inline u32 mc_enable_pb_0_f(u32 v) | ||
198 | { | ||
199 | return (v & 0x1) << 0; | ||
200 | } | ||
201 | static inline u32 mc_enable_pb_0_m(void) | ||
202 | { | ||
203 | return 0x1 << 0; | ||
204 | } | ||
205 | static inline u32 mc_enable_pb_0_v(u32 r) | ||
206 | { | ||
207 | return (r >> 0) & 0x1; | ||
208 | } | ||
209 | static inline u32 mc_enable_pb_0_enabled_v(void) | ||
210 | { | ||
211 | return 0x00000001; | ||
212 | } | ||
213 | static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) | ||
214 | { | ||
215 | return (v & 0x1) << (0 + i*1); | ||
216 | } | ||
217 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h new file mode 100644 index 00000000..e403abdb --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_pbdma_gm20b.h | |||
@@ -0,0 +1,437 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_pbdma_gm20b_h_ | ||
51 | #define _hw_pbdma_gm20b_h_ | ||
52 | |||
53 | static inline u32 pbdma_gp_entry1_r(void) | ||
54 | { | ||
55 | return 0x10000004; | ||
56 | } | ||
57 | static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) | ||
58 | { | ||
59 | return (r >> 0) & 0xff; | ||
60 | } | ||
61 | static inline u32 pbdma_gp_entry1_length_f(u32 v) | ||
62 | { | ||
63 | return (v & 0x1fffff) << 10; | ||
64 | } | ||
65 | static inline u32 pbdma_gp_entry1_length_v(u32 r) | ||
66 | { | ||
67 | return (r >> 10) & 0x1fffff; | ||
68 | } | ||
69 | static inline u32 pbdma_gp_base_r(u32 i) | ||
70 | { | ||
71 | return 0x00040048 + i*8192; | ||
72 | } | ||
73 | static inline u32 pbdma_gp_base__size_1_v(void) | ||
74 | { | ||
75 | return 0x00000001; | ||
76 | } | ||
77 | static inline u32 pbdma_gp_base_offset_f(u32 v) | ||
78 | { | ||
79 | return (v & 0x1fffffff) << 3; | ||
80 | } | ||
81 | static inline u32 pbdma_gp_base_rsvd_s(void) | ||
82 | { | ||
83 | return 3; | ||
84 | } | ||
85 | static inline u32 pbdma_gp_base_hi_r(u32 i) | ||
86 | { | ||
87 | return 0x0004004c + i*8192; | ||
88 | } | ||
89 | static inline u32 pbdma_gp_base_hi_offset_f(u32 v) | ||
90 | { | ||
91 | return (v & 0xff) << 0; | ||
92 | } | ||
93 | static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) | ||
94 | { | ||
95 | return (v & 0x1f) << 16; | ||
96 | } | ||
97 | static inline u32 pbdma_gp_fetch_r(u32 i) | ||
98 | { | ||
99 | return 0x00040050 + i*8192; | ||
100 | } | ||
101 | static inline u32 pbdma_gp_get_r(u32 i) | ||
102 | { | ||
103 | return 0x00040014 + i*8192; | ||
104 | } | ||
105 | static inline u32 pbdma_gp_put_r(u32 i) | ||
106 | { | ||
107 | return 0x00040000 + i*8192; | ||
108 | } | ||
109 | static inline u32 pbdma_pb_fetch_r(u32 i) | ||
110 | { | ||
111 | return 0x00040054 + i*8192; | ||
112 | } | ||
113 | static inline u32 pbdma_pb_fetch_hi_r(u32 i) | ||
114 | { | ||
115 | return 0x00040058 + i*8192; | ||
116 | } | ||
117 | static inline u32 pbdma_get_r(u32 i) | ||
118 | { | ||
119 | return 0x00040018 + i*8192; | ||
120 | } | ||
121 | static inline u32 pbdma_get_hi_r(u32 i) | ||
122 | { | ||
123 | return 0x0004001c + i*8192; | ||
124 | } | ||
125 | static inline u32 pbdma_put_r(u32 i) | ||
126 | { | ||
127 | return 0x0004005c + i*8192; | ||
128 | } | ||
129 | static inline u32 pbdma_put_hi_r(u32 i) | ||
130 | { | ||
131 | return 0x00040060 + i*8192; | ||
132 | } | ||
133 | static inline u32 pbdma_formats_r(u32 i) | ||
134 | { | ||
135 | return 0x0004009c + i*8192; | ||
136 | } | ||
137 | static inline u32 pbdma_formats_gp_fermi0_f(void) | ||
138 | { | ||
139 | return 0x0; | ||
140 | } | ||
141 | static inline u32 pbdma_formats_pb_fermi1_f(void) | ||
142 | { | ||
143 | return 0x100; | ||
144 | } | ||
145 | static inline u32 pbdma_formats_mp_fermi0_f(void) | ||
146 | { | ||
147 | return 0x0; | ||
148 | } | ||
149 | static inline u32 pbdma_pb_header_r(u32 i) | ||
150 | { | ||
151 | return 0x00040084 + i*8192; | ||
152 | } | ||
153 | static inline u32 pbdma_pb_header_priv_user_f(void) | ||
154 | { | ||
155 | return 0x0; | ||
156 | } | ||
157 | static inline u32 pbdma_pb_header_method_zero_f(void) | ||
158 | { | ||
159 | return 0x0; | ||
160 | } | ||
161 | static inline u32 pbdma_pb_header_subchannel_zero_f(void) | ||
162 | { | ||
163 | return 0x0; | ||
164 | } | ||
165 | static inline u32 pbdma_pb_header_level_main_f(void) | ||
166 | { | ||
167 | return 0x0; | ||
168 | } | ||
169 | static inline u32 pbdma_pb_header_first_true_f(void) | ||
170 | { | ||
171 | return 0x400000; | ||
172 | } | ||
173 | static inline u32 pbdma_pb_header_type_inc_f(void) | ||
174 | { | ||
175 | return 0x20000000; | ||
176 | } | ||
177 | static inline u32 pbdma_subdevice_r(u32 i) | ||
178 | { | ||
179 | return 0x00040094 + i*8192; | ||
180 | } | ||
181 | static inline u32 pbdma_subdevice_id_f(u32 v) | ||
182 | { | ||
183 | return (v & 0xfff) << 0; | ||
184 | } | ||
185 | static inline u32 pbdma_subdevice_status_active_f(void) | ||
186 | { | ||
187 | return 0x10000000; | ||
188 | } | ||
189 | static inline u32 pbdma_subdevice_channel_dma_enable_f(void) | ||
190 | { | ||
191 | return 0x20000000; | ||
192 | } | ||
193 | static inline u32 pbdma_method0_r(u32 i) | ||
194 | { | ||
195 | return 0x000400c0 + i*8192; | ||
196 | } | ||
197 | static inline u32 pbdma_data0_r(u32 i) | ||
198 | { | ||
199 | return 0x000400c4 + i*8192; | ||
200 | } | ||
201 | static inline u32 pbdma_target_r(u32 i) | ||
202 | { | ||
203 | return 0x000400ac + i*8192; | ||
204 | } | ||
205 | static inline u32 pbdma_target_engine_sw_f(void) | ||
206 | { | ||
207 | return 0x1f; | ||
208 | } | ||
209 | static inline u32 pbdma_acquire_r(u32 i) | ||
210 | { | ||
211 | return 0x00040030 + i*8192; | ||
212 | } | ||
213 | static inline u32 pbdma_acquire_retry_man_2_f(void) | ||
214 | { | ||
215 | return 0x2; | ||
216 | } | ||
217 | static inline u32 pbdma_acquire_retry_exp_2_f(void) | ||
218 | { | ||
219 | return 0x100; | ||
220 | } | ||
221 | static inline u32 pbdma_acquire_timeout_exp_max_f(void) | ||
222 | { | ||
223 | return 0x7800; | ||
224 | } | ||
225 | static inline u32 pbdma_acquire_timeout_man_max_f(void) | ||
226 | { | ||
227 | return 0x7fff8000; | ||
228 | } | ||
229 | static inline u32 pbdma_acquire_timeout_en_disable_f(void) | ||
230 | { | ||
231 | return 0x0; | ||
232 | } | ||
233 | static inline u32 pbdma_status_r(u32 i) | ||
234 | { | ||
235 | return 0x00040100 + i*8192; | ||
236 | } | ||
237 | static inline u32 pbdma_channel_r(u32 i) | ||
238 | { | ||
239 | return 0x00040120 + i*8192; | ||
240 | } | ||
241 | static inline u32 pbdma_signature_r(u32 i) | ||
242 | { | ||
243 | return 0x00040010 + i*8192; | ||
244 | } | ||
245 | static inline u32 pbdma_signature_hw_valid_f(void) | ||
246 | { | ||
247 | return 0xface; | ||
248 | } | ||
249 | static inline u32 pbdma_signature_sw_zero_f(void) | ||
250 | { | ||
251 | return 0x0; | ||
252 | } | ||
253 | static inline u32 pbdma_userd_r(u32 i) | ||
254 | { | ||
255 | return 0x00040008 + i*8192; | ||
256 | } | ||
257 | static inline u32 pbdma_userd_target_vid_mem_f(void) | ||
258 | { | ||
259 | return 0x0; | ||
260 | } | ||
261 | static inline u32 pbdma_userd_addr_f(u32 v) | ||
262 | { | ||
263 | return (v & 0x7fffff) << 9; | ||
264 | } | ||
265 | static inline u32 pbdma_userd_hi_r(u32 i) | ||
266 | { | ||
267 | return 0x0004000c + i*8192; | ||
268 | } | ||
269 | static inline u32 pbdma_userd_hi_addr_f(u32 v) | ||
270 | { | ||
271 | return (v & 0xff) << 0; | ||
272 | } | ||
273 | static inline u32 pbdma_hce_ctrl_r(u32 i) | ||
274 | { | ||
275 | return 0x000400e4 + i*8192; | ||
276 | } | ||
277 | static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) | ||
278 | { | ||
279 | return 0x20; | ||
280 | } | ||
281 | static inline u32 pbdma_intr_0_r(u32 i) | ||
282 | { | ||
283 | return 0x00040108 + i*8192; | ||
284 | } | ||
285 | static inline u32 pbdma_intr_0_memreq_v(u32 r) | ||
286 | { | ||
287 | return (r >> 0) & 0x1; | ||
288 | } | ||
289 | static inline u32 pbdma_intr_0_memreq_pending_f(void) | ||
290 | { | ||
291 | return 0x1; | ||
292 | } | ||
293 | static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) | ||
294 | { | ||
295 | return 0x2; | ||
296 | } | ||
297 | static inline u32 pbdma_intr_0_memack_extra_pending_f(void) | ||
298 | { | ||
299 | return 0x4; | ||
300 | } | ||
301 | static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) | ||
302 | { | ||
303 | return 0x8; | ||
304 | } | ||
305 | static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) | ||
306 | { | ||
307 | return 0x10; | ||
308 | } | ||
309 | static inline u32 pbdma_intr_0_memflush_pending_f(void) | ||
310 | { | ||
311 | return 0x20; | ||
312 | } | ||
313 | static inline u32 pbdma_intr_0_memop_pending_f(void) | ||
314 | { | ||
315 | return 0x40; | ||
316 | } | ||
317 | static inline u32 pbdma_intr_0_lbconnect_pending_f(void) | ||
318 | { | ||
319 | return 0x80; | ||
320 | } | ||
321 | static inline u32 pbdma_intr_0_lbreq_pending_f(void) | ||
322 | { | ||
323 | return 0x100; | ||
324 | } | ||
325 | static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) | ||
326 | { | ||
327 | return 0x200; | ||
328 | } | ||
329 | static inline u32 pbdma_intr_0_lback_extra_pending_f(void) | ||
330 | { | ||
331 | return 0x400; | ||
332 | } | ||
333 | static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) | ||
334 | { | ||
335 | return 0x800; | ||
336 | } | ||
337 | static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) | ||
338 | { | ||
339 | return 0x1000; | ||
340 | } | ||
341 | static inline u32 pbdma_intr_0_gpfifo_pending_f(void) | ||
342 | { | ||
343 | return 0x2000; | ||
344 | } | ||
345 | static inline u32 pbdma_intr_0_gpptr_pending_f(void) | ||
346 | { | ||
347 | return 0x4000; | ||
348 | } | ||
349 | static inline u32 pbdma_intr_0_gpentry_pending_f(void) | ||
350 | { | ||
351 | return 0x8000; | ||
352 | } | ||
353 | static inline u32 pbdma_intr_0_gpcrc_pending_f(void) | ||
354 | { | ||
355 | return 0x10000; | ||
356 | } | ||
357 | static inline u32 pbdma_intr_0_pbptr_pending_f(void) | ||
358 | { | ||
359 | return 0x20000; | ||
360 | } | ||
361 | static inline u32 pbdma_intr_0_pbentry_pending_f(void) | ||
362 | { | ||
363 | return 0x40000; | ||
364 | } | ||
365 | static inline u32 pbdma_intr_0_pbcrc_pending_f(void) | ||
366 | { | ||
367 | return 0x80000; | ||
368 | } | ||
369 | static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) | ||
370 | { | ||
371 | return 0x100000; | ||
372 | } | ||
373 | static inline u32 pbdma_intr_0_method_pending_f(void) | ||
374 | { | ||
375 | return 0x200000; | ||
376 | } | ||
377 | static inline u32 pbdma_intr_0_methodcrc_pending_f(void) | ||
378 | { | ||
379 | return 0x400000; | ||
380 | } | ||
381 | static inline u32 pbdma_intr_0_device_pending_f(void) | ||
382 | { | ||
383 | return 0x800000; | ||
384 | } | ||
385 | static inline u32 pbdma_intr_0_semaphore_pending_f(void) | ||
386 | { | ||
387 | return 0x2000000; | ||
388 | } | ||
389 | static inline u32 pbdma_intr_0_acquire_pending_f(void) | ||
390 | { | ||
391 | return 0x4000000; | ||
392 | } | ||
393 | static inline u32 pbdma_intr_0_pri_pending_f(void) | ||
394 | { | ||
395 | return 0x8000000; | ||
396 | } | ||
397 | static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) | ||
398 | { | ||
399 | return 0x20000000; | ||
400 | } | ||
401 | static inline u32 pbdma_intr_0_pbseg_pending_f(void) | ||
402 | { | ||
403 | return 0x40000000; | ||
404 | } | ||
405 | static inline u32 pbdma_intr_0_signature_pending_f(void) | ||
406 | { | ||
407 | return 0x80000000; | ||
408 | } | ||
409 | static inline u32 pbdma_intr_1_r(u32 i) | ||
410 | { | ||
411 | return 0x00040148 + i*8192; | ||
412 | } | ||
413 | static inline u32 pbdma_intr_en_0_r(u32 i) | ||
414 | { | ||
415 | return 0x0004010c + i*8192; | ||
416 | } | ||
417 | static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) | ||
418 | { | ||
419 | return 0x100; | ||
420 | } | ||
421 | static inline u32 pbdma_intr_en_1_r(u32 i) | ||
422 | { | ||
423 | return 0x0004014c + i*8192; | ||
424 | } | ||
425 | static inline u32 pbdma_intr_stall_r(u32 i) | ||
426 | { | ||
427 | return 0x0004013c + i*8192; | ||
428 | } | ||
429 | static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) | ||
430 | { | ||
431 | return 0x100; | ||
432 | } | ||
433 | static inline u32 pbdma_udma_nop_r(void) | ||
434 | { | ||
435 | return 0x00000008; | ||
436 | } | ||
437 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_pri_ringmaster_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_pri_ringmaster_gm20b.h new file mode 100644 index 00000000..930592db --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_pri_ringmaster_gm20b.h | |||
@@ -0,0 +1,145 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_pri_ringmaster_gm20b_h_ | ||
51 | #define _hw_pri_ringmaster_gm20b_h_ | ||
52 | |||
53 | static inline u32 pri_ringmaster_command_r(void) | ||
54 | { | ||
55 | return 0x0012004c; | ||
56 | } | ||
57 | static inline u32 pri_ringmaster_command_cmd_m(void) | ||
58 | { | ||
59 | return 0x3f << 0; | ||
60 | } | ||
61 | static inline u32 pri_ringmaster_command_cmd_v(u32 r) | ||
62 | { | ||
63 | return (r >> 0) & 0x3f; | ||
64 | } | ||
65 | static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) | ||
66 | { | ||
67 | return 0x00000000; | ||
68 | } | ||
69 | static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) | ||
70 | { | ||
71 | return 0x1; | ||
72 | } | ||
73 | static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) | ||
74 | { | ||
75 | return 0x2; | ||
76 | } | ||
77 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) | ||
78 | { | ||
79 | return 0x3; | ||
80 | } | ||
81 | static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) | ||
82 | { | ||
83 | return 0x0; | ||
84 | } | ||
85 | static inline u32 pri_ringmaster_command_data_r(void) | ||
86 | { | ||
87 | return 0x00120048; | ||
88 | } | ||
89 | static inline u32 pri_ringmaster_start_results_r(void) | ||
90 | { | ||
91 | return 0x00120050; | ||
92 | } | ||
93 | static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) | ||
94 | { | ||
95 | return (r >> 0) & 0x1; | ||
96 | } | ||
97 | static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) | ||
98 | { | ||
99 | return 0x00000001; | ||
100 | } | ||
101 | static inline u32 pri_ringmaster_intr_status0_r(void) | ||
102 | { | ||
103 | return 0x00120058; | ||
104 | } | ||
105 | static inline u32 pri_ringmaster_intr_status1_r(void) | ||
106 | { | ||
107 | return 0x0012005c; | ||
108 | } | ||
109 | static inline u32 pri_ringmaster_global_ctl_r(void) | ||
110 | { | ||
111 | return 0x00120060; | ||
112 | } | ||
113 | static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) | ||
114 | { | ||
115 | return 0x1; | ||
116 | } | ||
117 | static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) | ||
118 | { | ||
119 | return 0x0; | ||
120 | } | ||
121 | static inline u32 pri_ringmaster_enum_fbp_r(void) | ||
122 | { | ||
123 | return 0x00120074; | ||
124 | } | ||
125 | static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) | ||
126 | { | ||
127 | return (r >> 0) & 0x1f; | ||
128 | } | ||
129 | static inline u32 pri_ringmaster_enum_gpc_r(void) | ||
130 | { | ||
131 | return 0x00120078; | ||
132 | } | ||
133 | static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) | ||
134 | { | ||
135 | return (r >> 0) & 0x1f; | ||
136 | } | ||
137 | static inline u32 pri_ringmaster_enum_ltc_r(void) | ||
138 | { | ||
139 | return 0x0012006c; | ||
140 | } | ||
141 | static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) | ||
142 | { | ||
143 | return (r >> 0) & 0x1f; | ||
144 | } | ||
145 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_pri_ringstation_sys_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_pri_ringstation_sys_gm20b.h new file mode 100644 index 00000000..7170a287 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_pri_ringstation_sys_gm20b.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_pri_ringstation_sys_gm20b_h_ | ||
51 | #define _hw_pri_ringstation_sys_gm20b_h_ | ||
52 | |||
53 | static inline u32 pri_ringstation_sys_master_config_r(u32 i) | ||
54 | { | ||
55 | return 0x00122300 + i*4; | ||
56 | } | ||
57 | static inline u32 pri_ringstation_sys_decode_config_r(void) | ||
58 | { | ||
59 | return 0x00122204; | ||
60 | } | ||
61 | static inline u32 pri_ringstation_sys_decode_config_ring_m(void) | ||
62 | { | ||
63 | return 0x7 << 0; | ||
64 | } | ||
65 | static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) | ||
66 | { | ||
67 | return 0x1; | ||
68 | } | ||
69 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h new file mode 100644 index 00000000..f9531ae1 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_proj_gm20b.h | |||
@@ -0,0 +1,141 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_proj_gm20b_h_ | ||
51 | #define _hw_proj_gm20b_h_ | ||
52 | |||
53 | static inline u32 proj_gpc_base_v(void) | ||
54 | { | ||
55 | return 0x00500000; | ||
56 | } | ||
57 | static inline u32 proj_gpc_shared_base_v(void) | ||
58 | { | ||
59 | return 0x00418000; | ||
60 | } | ||
61 | static inline u32 proj_gpc_stride_v(void) | ||
62 | { | ||
63 | return 0x00008000; | ||
64 | } | ||
65 | static inline u32 proj_ltc_stride_v(void) | ||
66 | { | ||
67 | return 0x00002000; | ||
68 | } | ||
69 | static inline u32 proj_lts_stride_v(void) | ||
70 | { | ||
71 | return 0x00000200; | ||
72 | } | ||
73 | static inline u32 proj_ppc_in_gpc_base_v(void) | ||
74 | { | ||
75 | return 0x00003000; | ||
76 | } | ||
77 | static inline u32 proj_ppc_in_gpc_stride_v(void) | ||
78 | { | ||
79 | return 0x00000200; | ||
80 | } | ||
81 | static inline u32 proj_rop_base_v(void) | ||
82 | { | ||
83 | return 0x00410000; | ||
84 | } | ||
85 | static inline u32 proj_rop_shared_base_v(void) | ||
86 | { | ||
87 | return 0x00408800; | ||
88 | } | ||
89 | static inline u32 proj_rop_stride_v(void) | ||
90 | { | ||
91 | return 0x00000400; | ||
92 | } | ||
93 | static inline u32 proj_tpc_in_gpc_base_v(void) | ||
94 | { | ||
95 | return 0x00004000; | ||
96 | } | ||
97 | static inline u32 proj_tpc_in_gpc_stride_v(void) | ||
98 | { | ||
99 | return 0x00000800; | ||
100 | } | ||
101 | static inline u32 proj_tpc_in_gpc_shared_base_v(void) | ||
102 | { | ||
103 | return 0x00001800; | ||
104 | } | ||
105 | static inline u32 proj_host_num_pbdma_v(void) | ||
106 | { | ||
107 | return 0x00000001; | ||
108 | } | ||
109 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) | ||
110 | { | ||
111 | return 0x00000002; | ||
112 | } | ||
113 | static inline u32 proj_scal_litter_num_fbps_v(void) | ||
114 | { | ||
115 | return 0x00000001; | ||
116 | } | ||
117 | static inline u32 proj_scal_litter_num_gpcs_v(void) | ||
118 | { | ||
119 | return 0x00000001; | ||
120 | } | ||
121 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) | ||
122 | { | ||
123 | return 0x00000001; | ||
124 | } | ||
125 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) | ||
126 | { | ||
127 | return 0x00000002; | ||
128 | } | ||
129 | static inline u32 proj_scal_litter_num_zcull_banks_v(void) | ||
130 | { | ||
131 | return 0x00000004; | ||
132 | } | ||
133 | static inline u32 proj_scal_max_gpcs_v(void) | ||
134 | { | ||
135 | return 0x00000020; | ||
136 | } | ||
137 | static inline u32 proj_scal_max_tpc_per_gpc_v(void) | ||
138 | { | ||
139 | return 0x00000008; | ||
140 | } | ||
141 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_pwr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_pwr_gm20b.h new file mode 100644 index 00000000..3af9cda8 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_pwr_gm20b.h | |||
@@ -0,0 +1,725 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_pwr_gm20b_h_ | ||
51 | #define _hw_pwr_gm20b_h_ | ||
52 | |||
53 | static inline u32 pwr_falcon_irqsset_r(void) | ||
54 | { | ||
55 | return 0x0010a000; | ||
56 | } | ||
57 | static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) | ||
58 | { | ||
59 | return 0x40; | ||
60 | } | ||
61 | static inline u32 pwr_falcon_irqsclr_r(void) | ||
62 | { | ||
63 | return 0x0010a004; | ||
64 | } | ||
65 | static inline u32 pwr_falcon_irqstat_r(void) | ||
66 | { | ||
67 | return 0x0010a008; | ||
68 | } | ||
69 | static inline u32 pwr_falcon_irqstat_halt_true_f(void) | ||
70 | { | ||
71 | return 0x10; | ||
72 | } | ||
73 | static inline u32 pwr_falcon_irqstat_exterr_true_f(void) | ||
74 | { | ||
75 | return 0x20; | ||
76 | } | ||
77 | static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) | ||
78 | { | ||
79 | return 0x40; | ||
80 | } | ||
81 | static inline u32 pwr_falcon_irqmode_r(void) | ||
82 | { | ||
83 | return 0x0010a00c; | ||
84 | } | ||
85 | static inline u32 pwr_falcon_irqmset_r(void) | ||
86 | { | ||
87 | return 0x0010a010; | ||
88 | } | ||
89 | static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) | ||
90 | { | ||
91 | return (v & 0x1) << 0; | ||
92 | } | ||
93 | static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) | ||
94 | { | ||
95 | return (v & 0x1) << 1; | ||
96 | } | ||
97 | static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) | ||
98 | { | ||
99 | return (v & 0x1) << 2; | ||
100 | } | ||
101 | static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) | ||
102 | { | ||
103 | return (v & 0x1) << 3; | ||
104 | } | ||
105 | static inline u32 pwr_falcon_irqmset_halt_f(u32 v) | ||
106 | { | ||
107 | return (v & 0x1) << 4; | ||
108 | } | ||
109 | static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) | ||
110 | { | ||
111 | return (v & 0x1) << 5; | ||
112 | } | ||
113 | static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) | ||
114 | { | ||
115 | return (v & 0x1) << 6; | ||
116 | } | ||
117 | static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) | ||
118 | { | ||
119 | return (v & 0x1) << 7; | ||
120 | } | ||
121 | static inline u32 pwr_falcon_irqmclr_r(void) | ||
122 | { | ||
123 | return 0x0010a014; | ||
124 | } | ||
125 | static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) | ||
126 | { | ||
127 | return (v & 0x1) << 0; | ||
128 | } | ||
129 | static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x1) << 1; | ||
132 | } | ||
133 | static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) | ||
134 | { | ||
135 | return (v & 0x1) << 2; | ||
136 | } | ||
137 | static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) | ||
138 | { | ||
139 | return (v & 0x1) << 3; | ||
140 | } | ||
141 | static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) | ||
142 | { | ||
143 | return (v & 0x1) << 4; | ||
144 | } | ||
145 | static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) | ||
146 | { | ||
147 | return (v & 0x1) << 5; | ||
148 | } | ||
149 | static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) | ||
150 | { | ||
151 | return (v & 0x1) << 6; | ||
152 | } | ||
153 | static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) | ||
154 | { | ||
155 | return (v & 0x1) << 7; | ||
156 | } | ||
157 | static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) | ||
158 | { | ||
159 | return (v & 0xff) << 8; | ||
160 | } | ||
161 | static inline u32 pwr_falcon_irqmask_r(void) | ||
162 | { | ||
163 | return 0x0010a018; | ||
164 | } | ||
165 | static inline u32 pwr_falcon_irqdest_r(void) | ||
166 | { | ||
167 | return 0x0010a01c; | ||
168 | } | ||
169 | static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x1) << 0; | ||
172 | } | ||
173 | static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) | ||
174 | { | ||
175 | return (v & 0x1) << 1; | ||
176 | } | ||
177 | static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) | ||
178 | { | ||
179 | return (v & 0x1) << 2; | ||
180 | } | ||
181 | static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) | ||
182 | { | ||
183 | return (v & 0x1) << 3; | ||
184 | } | ||
185 | static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) | ||
186 | { | ||
187 | return (v & 0x1) << 4; | ||
188 | } | ||
189 | static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) | ||
190 | { | ||
191 | return (v & 0x1) << 5; | ||
192 | } | ||
193 | static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) | ||
194 | { | ||
195 | return (v & 0x1) << 6; | ||
196 | } | ||
197 | static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) | ||
198 | { | ||
199 | return (v & 0x1) << 7; | ||
200 | } | ||
201 | static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) | ||
202 | { | ||
203 | return (v & 0xff) << 8; | ||
204 | } | ||
205 | static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) | ||
206 | { | ||
207 | return (v & 0x1) << 16; | ||
208 | } | ||
209 | static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) | ||
210 | { | ||
211 | return (v & 0x1) << 17; | ||
212 | } | ||
213 | static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) | ||
214 | { | ||
215 | return (v & 0x1) << 18; | ||
216 | } | ||
217 | static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) | ||
218 | { | ||
219 | return (v & 0x1) << 19; | ||
220 | } | ||
221 | static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) | ||
222 | { | ||
223 | return (v & 0x1) << 20; | ||
224 | } | ||
225 | static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) | ||
226 | { | ||
227 | return (v & 0x1) << 21; | ||
228 | } | ||
229 | static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) | ||
230 | { | ||
231 | return (v & 0x1) << 22; | ||
232 | } | ||
233 | static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) | ||
234 | { | ||
235 | return (v & 0x1) << 23; | ||
236 | } | ||
237 | static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) | ||
238 | { | ||
239 | return (v & 0xff) << 24; | ||
240 | } | ||
241 | static inline u32 pwr_falcon_curctx_r(void) | ||
242 | { | ||
243 | return 0x0010a050; | ||
244 | } | ||
245 | static inline u32 pwr_falcon_nxtctx_r(void) | ||
246 | { | ||
247 | return 0x0010a054; | ||
248 | } | ||
249 | static inline u32 pwr_falcon_mailbox0_r(void) | ||
250 | { | ||
251 | return 0x0010a040; | ||
252 | } | ||
253 | static inline u32 pwr_falcon_mailbox1_r(void) | ||
254 | { | ||
255 | return 0x0010a044; | ||
256 | } | ||
257 | static inline u32 pwr_falcon_itfen_r(void) | ||
258 | { | ||
259 | return 0x0010a048; | ||
260 | } | ||
261 | static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) | ||
262 | { | ||
263 | return 0x1; | ||
264 | } | ||
265 | static inline u32 pwr_falcon_idlestate_r(void) | ||
266 | { | ||
267 | return 0x0010a04c; | ||
268 | } | ||
269 | static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) | ||
270 | { | ||
271 | return (r >> 0) & 0x1; | ||
272 | } | ||
273 | static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) | ||
274 | { | ||
275 | return (r >> 1) & 0x7fff; | ||
276 | } | ||
277 | static inline u32 pwr_falcon_os_r(void) | ||
278 | { | ||
279 | return 0x0010a080; | ||
280 | } | ||
281 | static inline u32 pwr_falcon_engctl_r(void) | ||
282 | { | ||
283 | return 0x0010a0a4; | ||
284 | } | ||
285 | static inline u32 pwr_falcon_cpuctl_r(void) | ||
286 | { | ||
287 | return 0x0010a100; | ||
288 | } | ||
289 | static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) | ||
290 | { | ||
291 | return (v & 0x1) << 1; | ||
292 | } | ||
293 | static inline u32 pwr_falcon_bootvec_r(void) | ||
294 | { | ||
295 | return 0x0010a104; | ||
296 | } | ||
297 | static inline u32 pwr_falcon_bootvec_vec_f(u32 v) | ||
298 | { | ||
299 | return (v & 0xffffffff) << 0; | ||
300 | } | ||
301 | static inline u32 pwr_falcon_hwcfg_r(void) | ||
302 | { | ||
303 | return 0x0010a108; | ||
304 | } | ||
305 | static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) | ||
306 | { | ||
307 | return (r >> 0) & 0x1ff; | ||
308 | } | ||
309 | static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) | ||
310 | { | ||
311 | return (r >> 9) & 0x1ff; | ||
312 | } | ||
313 | static inline u32 pwr_falcon_dmatrfbase_r(void) | ||
314 | { | ||
315 | return 0x0010a110; | ||
316 | } | ||
317 | static inline u32 pwr_falcon_dmatrfmoffs_r(void) | ||
318 | { | ||
319 | return 0x0010a114; | ||
320 | } | ||
321 | static inline u32 pwr_falcon_dmatrfcmd_r(void) | ||
322 | { | ||
323 | return 0x0010a118; | ||
324 | } | ||
325 | static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) | ||
326 | { | ||
327 | return (v & 0x1) << 4; | ||
328 | } | ||
329 | static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) | ||
330 | { | ||
331 | return (v & 0x1) << 5; | ||
332 | } | ||
333 | static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) | ||
334 | { | ||
335 | return (v & 0x7) << 8; | ||
336 | } | ||
337 | static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) | ||
338 | { | ||
339 | return (v & 0x7) << 12; | ||
340 | } | ||
341 | static inline u32 pwr_falcon_dmatrffboffs_r(void) | ||
342 | { | ||
343 | return 0x0010a11c; | ||
344 | } | ||
345 | static inline u32 pwr_falcon_exterraddr_r(void) | ||
346 | { | ||
347 | return 0x0010a168; | ||
348 | } | ||
349 | static inline u32 pwr_falcon_exterrstat_r(void) | ||
350 | { | ||
351 | return 0x0010a16c; | ||
352 | } | ||
353 | static inline u32 pwr_falcon_exterrstat_valid_m(void) | ||
354 | { | ||
355 | return 0x1 << 31; | ||
356 | } | ||
357 | static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) | ||
358 | { | ||
359 | return (r >> 31) & 0x1; | ||
360 | } | ||
361 | static inline u32 pwr_falcon_exterrstat_valid_true_v(void) | ||
362 | { | ||
363 | return 0x00000001; | ||
364 | } | ||
365 | static inline u32 pwr_pmu_falcon_icd_cmd_r(void) | ||
366 | { | ||
367 | return 0x0010a200; | ||
368 | } | ||
369 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) | ||
370 | { | ||
371 | return 4; | ||
372 | } | ||
373 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) | ||
374 | { | ||
375 | return (v & 0xf) << 0; | ||
376 | } | ||
377 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) | ||
378 | { | ||
379 | return 0xf << 0; | ||
380 | } | ||
381 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) | ||
382 | { | ||
383 | return (r >> 0) & 0xf; | ||
384 | } | ||
385 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) | ||
386 | { | ||
387 | return 0x8; | ||
388 | } | ||
389 | static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) | ||
390 | { | ||
391 | return 0xe; | ||
392 | } | ||
393 | static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) | ||
394 | { | ||
395 | return (v & 0x1f) << 8; | ||
396 | } | ||
397 | static inline u32 pwr_pmu_falcon_icd_rdata_r(void) | ||
398 | { | ||
399 | return 0x0010a20c; | ||
400 | } | ||
401 | static inline u32 pwr_falcon_dmemc_r(u32 i) | ||
402 | { | ||
403 | return 0x0010a1c0 + i*8; | ||
404 | } | ||
405 | static inline u32 pwr_falcon_dmemc_offs_f(u32 v) | ||
406 | { | ||
407 | return (v & 0x3f) << 2; | ||
408 | } | ||
409 | static inline u32 pwr_falcon_dmemc_offs_m(void) | ||
410 | { | ||
411 | return 0x3f << 2; | ||
412 | } | ||
413 | static inline u32 pwr_falcon_dmemc_blk_f(u32 v) | ||
414 | { | ||
415 | return (v & 0xff) << 8; | ||
416 | } | ||
417 | static inline u32 pwr_falcon_dmemc_blk_m(void) | ||
418 | { | ||
419 | return 0xff << 8; | ||
420 | } | ||
421 | static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) | ||
422 | { | ||
423 | return (v & 0x1) << 24; | ||
424 | } | ||
425 | static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) | ||
426 | { | ||
427 | return (v & 0x1) << 25; | ||
428 | } | ||
429 | static inline u32 pwr_falcon_dmemd_r(u32 i) | ||
430 | { | ||
431 | return 0x0010a1c4 + i*8; | ||
432 | } | ||
433 | static inline u32 pwr_pmu_new_instblk_r(void) | ||
434 | { | ||
435 | return 0x0010a480; | ||
436 | } | ||
437 | static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) | ||
438 | { | ||
439 | return (v & 0xfffffff) << 0; | ||
440 | } | ||
441 | static inline u32 pwr_pmu_new_instblk_target_fb_f(void) | ||
442 | { | ||
443 | return 0x0; | ||
444 | } | ||
445 | static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) | ||
446 | { | ||
447 | return 0x20000000; | ||
448 | } | ||
449 | static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) | ||
450 | { | ||
451 | return (v & 0x1) << 30; | ||
452 | } | ||
453 | static inline u32 pwr_pmu_mutex_id_r(void) | ||
454 | { | ||
455 | return 0x0010a488; | ||
456 | } | ||
457 | static inline u32 pwr_pmu_mutex_id_value_v(u32 r) | ||
458 | { | ||
459 | return (r >> 0) & 0xff; | ||
460 | } | ||
461 | static inline u32 pwr_pmu_mutex_id_value_init_v(void) | ||
462 | { | ||
463 | return 0x00000000; | ||
464 | } | ||
465 | static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) | ||
466 | { | ||
467 | return 0x000000ff; | ||
468 | } | ||
469 | static inline u32 pwr_pmu_mutex_id_release_r(void) | ||
470 | { | ||
471 | return 0x0010a48c; | ||
472 | } | ||
473 | static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) | ||
474 | { | ||
475 | return (v & 0xff) << 0; | ||
476 | } | ||
477 | static inline u32 pwr_pmu_mutex_id_release_value_m(void) | ||
478 | { | ||
479 | return 0xff << 0; | ||
480 | } | ||
481 | static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) | ||
482 | { | ||
483 | return 0x00000000; | ||
484 | } | ||
485 | static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) | ||
486 | { | ||
487 | return 0x0; | ||
488 | } | ||
489 | static inline u32 pwr_pmu_mutex_r(u32 i) | ||
490 | { | ||
491 | return 0x0010a580 + i*4; | ||
492 | } | ||
493 | static inline u32 pwr_pmu_mutex__size_1_v(void) | ||
494 | { | ||
495 | return 0x00000010; | ||
496 | } | ||
497 | static inline u32 pwr_pmu_mutex_value_f(u32 v) | ||
498 | { | ||
499 | return (v & 0xff) << 0; | ||
500 | } | ||
501 | static inline u32 pwr_pmu_mutex_value_v(u32 r) | ||
502 | { | ||
503 | return (r >> 0) & 0xff; | ||
504 | } | ||
505 | static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) | ||
506 | { | ||
507 | return 0x0; | ||
508 | } | ||
509 | static inline u32 pwr_pmu_queue_head_r(u32 i) | ||
510 | { | ||
511 | return 0x0010a4a0 + i*4; | ||
512 | } | ||
513 | static inline u32 pwr_pmu_queue_head__size_1_v(void) | ||
514 | { | ||
515 | return 0x00000004; | ||
516 | } | ||
517 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) | ||
518 | { | ||
519 | return (v & 0xffffffff) << 0; | ||
520 | } | ||
521 | static inline u32 pwr_pmu_queue_head_address_v(u32 r) | ||
522 | { | ||
523 | return (r >> 0) & 0xffffffff; | ||
524 | } | ||
525 | static inline u32 pwr_pmu_queue_tail_r(u32 i) | ||
526 | { | ||
527 | return 0x0010a4b0 + i*4; | ||
528 | } | ||
529 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) | ||
530 | { | ||
531 | return 0x00000004; | ||
532 | } | ||
533 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) | ||
534 | { | ||
535 | return (v & 0xffffffff) << 0; | ||
536 | } | ||
537 | static inline u32 pwr_pmu_queue_tail_address_v(u32 r) | ||
538 | { | ||
539 | return (r >> 0) & 0xffffffff; | ||
540 | } | ||
541 | static inline u32 pwr_pmu_msgq_head_r(void) | ||
542 | { | ||
543 | return 0x0010a4c8; | ||
544 | } | ||
545 | static inline u32 pwr_pmu_msgq_head_val_f(u32 v) | ||
546 | { | ||
547 | return (v & 0xffffffff) << 0; | ||
548 | } | ||
549 | static inline u32 pwr_pmu_msgq_head_val_v(u32 r) | ||
550 | { | ||
551 | return (r >> 0) & 0xffffffff; | ||
552 | } | ||
553 | static inline u32 pwr_pmu_msgq_tail_r(void) | ||
554 | { | ||
555 | return 0x0010a4cc; | ||
556 | } | ||
557 | static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) | ||
558 | { | ||
559 | return (v & 0xffffffff) << 0; | ||
560 | } | ||
561 | static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) | ||
562 | { | ||
563 | return (r >> 0) & 0xffffffff; | ||
564 | } | ||
565 | static inline u32 pwr_pmu_idle_mask_r(u32 i) | ||
566 | { | ||
567 | return 0x0010a504 + i*16; | ||
568 | } | ||
569 | static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) | ||
570 | { | ||
571 | return 0x1; | ||
572 | } | ||
573 | static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) | ||
574 | { | ||
575 | return 0x200000; | ||
576 | } | ||
577 | static inline u32 pwr_pmu_idle_count_r(u32 i) | ||
578 | { | ||
579 | return 0x0010a508 + i*16; | ||
580 | } | ||
581 | static inline u32 pwr_pmu_idle_count_value_f(u32 v) | ||
582 | { | ||
583 | return (v & 0x7fffffff) << 0; | ||
584 | } | ||
585 | static inline u32 pwr_pmu_idle_count_value_v(u32 r) | ||
586 | { | ||
587 | return (r >> 0) & 0x7fffffff; | ||
588 | } | ||
589 | static inline u32 pwr_pmu_idle_count_reset_f(u32 v) | ||
590 | { | ||
591 | return (v & 0x1) << 31; | ||
592 | } | ||
593 | static inline u32 pwr_pmu_idle_ctrl_r(u32 i) | ||
594 | { | ||
595 | return 0x0010a50c + i*16; | ||
596 | } | ||
597 | static inline u32 pwr_pmu_idle_ctrl_value_m(void) | ||
598 | { | ||
599 | return 0x3 << 0; | ||
600 | } | ||
601 | static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) | ||
602 | { | ||
603 | return 0x2; | ||
604 | } | ||
605 | static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) | ||
606 | { | ||
607 | return 0x3; | ||
608 | } | ||
609 | static inline u32 pwr_pmu_idle_ctrl_filter_m(void) | ||
610 | { | ||
611 | return 0x1 << 2; | ||
612 | } | ||
613 | static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) | ||
614 | { | ||
615 | return 0x0; | ||
616 | } | ||
617 | static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) | ||
618 | { | ||
619 | return 0x0010a9f0 + i*8; | ||
620 | } | ||
621 | static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) | ||
622 | { | ||
623 | return 0x0010a9f4 + i*8; | ||
624 | } | ||
625 | static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) | ||
626 | { | ||
627 | return 0x0010aa30 + i*8; | ||
628 | } | ||
629 | static inline u32 pwr_pmu_debug_r(u32 i) | ||
630 | { | ||
631 | return 0x0010a5c0 + i*4; | ||
632 | } | ||
633 | static inline u32 pwr_pmu_debug__size_1_v(void) | ||
634 | { | ||
635 | return 0x00000004; | ||
636 | } | ||
637 | static inline u32 pwr_pmu_mailbox_r(u32 i) | ||
638 | { | ||
639 | return 0x0010a450 + i*4; | ||
640 | } | ||
641 | static inline u32 pwr_pmu_mailbox__size_1_v(void) | ||
642 | { | ||
643 | return 0x0000000c; | ||
644 | } | ||
645 | static inline u32 pwr_pmu_bar0_addr_r(void) | ||
646 | { | ||
647 | return 0x0010a7a0; | ||
648 | } | ||
649 | static inline u32 pwr_pmu_bar0_data_r(void) | ||
650 | { | ||
651 | return 0x0010a7a4; | ||
652 | } | ||
653 | static inline u32 pwr_pmu_bar0_ctl_r(void) | ||
654 | { | ||
655 | return 0x0010a7ac; | ||
656 | } | ||
657 | static inline u32 pwr_pmu_bar0_timeout_r(void) | ||
658 | { | ||
659 | return 0x0010a7a8; | ||
660 | } | ||
661 | static inline u32 pwr_pmu_bar0_fecs_error_r(void) | ||
662 | { | ||
663 | return 0x0010a988; | ||
664 | } | ||
665 | static inline u32 pwr_pmu_bar0_error_status_r(void) | ||
666 | { | ||
667 | return 0x0010a7b0; | ||
668 | } | ||
669 | static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) | ||
670 | { | ||
671 | return 0x0010a6c0 + i*4; | ||
672 | } | ||
673 | static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) | ||
674 | { | ||
675 | return 0x0010a6e8 + i*4; | ||
676 | } | ||
677 | static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) | ||
678 | { | ||
679 | return 0x0010a710 + i*4; | ||
680 | } | ||
681 | static inline u32 pwr_pmu_pg_intren_r(u32 i) | ||
682 | { | ||
683 | return 0x0010a760 + i*4; | ||
684 | } | ||
685 | static inline u32 pwr_fbif_transcfg_r(u32 i) | ||
686 | { | ||
687 | return 0x0010ae00 + i*4; | ||
688 | } | ||
689 | static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) | ||
690 | { | ||
691 | return 0x0; | ||
692 | } | ||
693 | static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) | ||
694 | { | ||
695 | return 0x1; | ||
696 | } | ||
697 | static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) | ||
698 | { | ||
699 | return 0x2; | ||
700 | } | ||
701 | static inline u32 pwr_fbif_transcfg_mem_type_s(void) | ||
702 | { | ||
703 | return 1; | ||
704 | } | ||
705 | static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) | ||
706 | { | ||
707 | return (v & 0x1) << 2; | ||
708 | } | ||
709 | static inline u32 pwr_fbif_transcfg_mem_type_m(void) | ||
710 | { | ||
711 | return 0x1 << 2; | ||
712 | } | ||
713 | static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) | ||
714 | { | ||
715 | return (r >> 2) & 0x1; | ||
716 | } | ||
717 | static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) | ||
718 | { | ||
719 | return 0x0; | ||
720 | } | ||
721 | static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) | ||
722 | { | ||
723 | return 0x4; | ||
724 | } | ||
725 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h new file mode 100644 index 00000000..6debecda --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h | |||
@@ -0,0 +1,385 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_ram_gm20b_h_ | ||
51 | #define _hw_ram_gm20b_h_ | ||
52 | |||
53 | static inline u32 ram_in_ramfc_s(void) | ||
54 | { | ||
55 | return 4096; | ||
56 | } | ||
57 | static inline u32 ram_in_ramfc_w(void) | ||
58 | { | ||
59 | return 0; | ||
60 | } | ||
61 | static inline u32 ram_in_page_dir_base_target_f(u32 v) | ||
62 | { | ||
63 | return (v & 0x3) << 0; | ||
64 | } | ||
65 | static inline u32 ram_in_page_dir_base_target_w(void) | ||
66 | { | ||
67 | return 128; | ||
68 | } | ||
69 | static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) | ||
70 | { | ||
71 | return 0x0; | ||
72 | } | ||
73 | static inline u32 ram_in_page_dir_base_vol_w(void) | ||
74 | { | ||
75 | return 128; | ||
76 | } | ||
77 | static inline u32 ram_in_page_dir_base_vol_true_f(void) | ||
78 | { | ||
79 | return 0x4; | ||
80 | } | ||
81 | static inline u32 ram_in_page_dir_base_lo_f(u32 v) | ||
82 | { | ||
83 | return (v & 0xfffff) << 12; | ||
84 | } | ||
85 | static inline u32 ram_in_page_dir_base_lo_w(void) | ||
86 | { | ||
87 | return 128; | ||
88 | } | ||
89 | static inline u32 ram_in_page_dir_base_hi_f(u32 v) | ||
90 | { | ||
91 | return (v & 0xff) << 0; | ||
92 | } | ||
93 | static inline u32 ram_in_page_dir_base_hi_w(void) | ||
94 | { | ||
95 | return 129; | ||
96 | } | ||
97 | static inline u32 ram_in_adr_limit_lo_f(u32 v) | ||
98 | { | ||
99 | return (v & 0xfffff) << 12; | ||
100 | } | ||
101 | static inline u32 ram_in_adr_limit_lo_w(void) | ||
102 | { | ||
103 | return 130; | ||
104 | } | ||
105 | static inline u32 ram_in_adr_limit_hi_f(u32 v) | ||
106 | { | ||
107 | return (v & 0xff) << 0; | ||
108 | } | ||
109 | static inline u32 ram_in_adr_limit_hi_w(void) | ||
110 | { | ||
111 | return 131; | ||
112 | } | ||
113 | static inline u32 ram_in_engine_cs_w(void) | ||
114 | { | ||
115 | return 132; | ||
116 | } | ||
117 | static inline u32 ram_in_engine_cs_wfi_v(void) | ||
118 | { | ||
119 | return 0x00000000; | ||
120 | } | ||
121 | static inline u32 ram_in_engine_cs_wfi_f(void) | ||
122 | { | ||
123 | return 0x0; | ||
124 | } | ||
125 | static inline u32 ram_in_engine_cs_fg_v(void) | ||
126 | { | ||
127 | return 0x00000001; | ||
128 | } | ||
129 | static inline u32 ram_in_engine_cs_fg_f(void) | ||
130 | { | ||
131 | return 0x8; | ||
132 | } | ||
133 | static inline u32 ram_in_gr_cs_w(void) | ||
134 | { | ||
135 | return 132; | ||
136 | } | ||
137 | static inline u32 ram_in_gr_cs_wfi_f(void) | ||
138 | { | ||
139 | return 0x0; | ||
140 | } | ||
141 | static inline u32 ram_in_gr_wfi_target_w(void) | ||
142 | { | ||
143 | return 132; | ||
144 | } | ||
145 | static inline u32 ram_in_gr_wfi_mode_w(void) | ||
146 | { | ||
147 | return 132; | ||
148 | } | ||
149 | static inline u32 ram_in_gr_wfi_mode_physical_v(void) | ||
150 | { | ||
151 | return 0x00000000; | ||
152 | } | ||
153 | static inline u32 ram_in_gr_wfi_mode_physical_f(void) | ||
154 | { | ||
155 | return 0x0; | ||
156 | } | ||
157 | static inline u32 ram_in_gr_wfi_mode_virtual_v(void) | ||
158 | { | ||
159 | return 0x00000001; | ||
160 | } | ||
161 | static inline u32 ram_in_gr_wfi_mode_virtual_f(void) | ||
162 | { | ||
163 | return 0x4; | ||
164 | } | ||
165 | static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) | ||
166 | { | ||
167 | return (v & 0xfffff) << 12; | ||
168 | } | ||
169 | static inline u32 ram_in_gr_wfi_ptr_lo_w(void) | ||
170 | { | ||
171 | return 132; | ||
172 | } | ||
173 | static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) | ||
174 | { | ||
175 | return (v & 0xff) << 0; | ||
176 | } | ||
177 | static inline u32 ram_in_gr_wfi_ptr_hi_w(void) | ||
178 | { | ||
179 | return 133; | ||
180 | } | ||
181 | static inline u32 ram_in_base_shift_v(void) | ||
182 | { | ||
183 | return 0x0000000c; | ||
184 | } | ||
185 | static inline u32 ram_in_alloc_size_v(void) | ||
186 | { | ||
187 | return 0x00001000; | ||
188 | } | ||
189 | static inline u32 ram_fc_size_val_v(void) | ||
190 | { | ||
191 | return 0x00000200; | ||
192 | } | ||
193 | static inline u32 ram_fc_gp_put_w(void) | ||
194 | { | ||
195 | return 0; | ||
196 | } | ||
197 | static inline u32 ram_fc_userd_w(void) | ||
198 | { | ||
199 | return 2; | ||
200 | } | ||
201 | static inline u32 ram_fc_userd_hi_w(void) | ||
202 | { | ||
203 | return 3; | ||
204 | } | ||
205 | static inline u32 ram_fc_signature_w(void) | ||
206 | { | ||
207 | return 4; | ||
208 | } | ||
209 | static inline u32 ram_fc_gp_get_w(void) | ||
210 | { | ||
211 | return 5; | ||
212 | } | ||
213 | static inline u32 ram_fc_pb_get_w(void) | ||
214 | { | ||
215 | return 6; | ||
216 | } | ||
217 | static inline u32 ram_fc_pb_get_hi_w(void) | ||
218 | { | ||
219 | return 7; | ||
220 | } | ||
221 | static inline u32 ram_fc_pb_top_level_get_w(void) | ||
222 | { | ||
223 | return 8; | ||
224 | } | ||
225 | static inline u32 ram_fc_pb_top_level_get_hi_w(void) | ||
226 | { | ||
227 | return 9; | ||
228 | } | ||
229 | static inline u32 ram_fc_acquire_w(void) | ||
230 | { | ||
231 | return 12; | ||
232 | } | ||
233 | static inline u32 ram_fc_semaphorea_w(void) | ||
234 | { | ||
235 | return 14; | ||
236 | } | ||
237 | static inline u32 ram_fc_semaphoreb_w(void) | ||
238 | { | ||
239 | return 15; | ||
240 | } | ||
241 | static inline u32 ram_fc_semaphorec_w(void) | ||
242 | { | ||
243 | return 16; | ||
244 | } | ||
245 | static inline u32 ram_fc_semaphored_w(void) | ||
246 | { | ||
247 | return 17; | ||
248 | } | ||
249 | static inline u32 ram_fc_gp_base_w(void) | ||
250 | { | ||
251 | return 18; | ||
252 | } | ||
253 | static inline u32 ram_fc_gp_base_hi_w(void) | ||
254 | { | ||
255 | return 19; | ||
256 | } | ||
257 | static inline u32 ram_fc_gp_fetch_w(void) | ||
258 | { | ||
259 | return 20; | ||
260 | } | ||
261 | static inline u32 ram_fc_pb_fetch_w(void) | ||
262 | { | ||
263 | return 21; | ||
264 | } | ||
265 | static inline u32 ram_fc_pb_fetch_hi_w(void) | ||
266 | { | ||
267 | return 22; | ||
268 | } | ||
269 | static inline u32 ram_fc_pb_put_w(void) | ||
270 | { | ||
271 | return 23; | ||
272 | } | ||
273 | static inline u32 ram_fc_pb_put_hi_w(void) | ||
274 | { | ||
275 | return 24; | ||
276 | } | ||
277 | static inline u32 ram_fc_pb_header_w(void) | ||
278 | { | ||
279 | return 33; | ||
280 | } | ||
281 | static inline u32 ram_fc_pb_count_w(void) | ||
282 | { | ||
283 | return 34; | ||
284 | } | ||
285 | static inline u32 ram_fc_subdevice_w(void) | ||
286 | { | ||
287 | return 37; | ||
288 | } | ||
289 | static inline u32 ram_fc_formats_w(void) | ||
290 | { | ||
291 | return 39; | ||
292 | } | ||
293 | static inline u32 ram_fc_syncpointa_w(void) | ||
294 | { | ||
295 | return 41; | ||
296 | } | ||
297 | static inline u32 ram_fc_syncpointb_w(void) | ||
298 | { | ||
299 | return 42; | ||
300 | } | ||
301 | static inline u32 ram_fc_target_w(void) | ||
302 | { | ||
303 | return 43; | ||
304 | } | ||
305 | static inline u32 ram_fc_hce_ctrl_w(void) | ||
306 | { | ||
307 | return 57; | ||
308 | } | ||
309 | static inline u32 ram_fc_chid_w(void) | ||
310 | { | ||
311 | return 58; | ||
312 | } | ||
313 | static inline u32 ram_fc_chid_id_f(u32 v) | ||
314 | { | ||
315 | return (v & 0xfff) << 0; | ||
316 | } | ||
317 | static inline u32 ram_fc_chid_id_w(void) | ||
318 | { | ||
319 | return 0; | ||
320 | } | ||
321 | static inline u32 ram_fc_pb_timeslice_w(void) | ||
322 | { | ||
323 | return 62; | ||
324 | } | ||
325 | static inline u32 ram_userd_base_shift_v(void) | ||
326 | { | ||
327 | return 0x00000009; | ||
328 | } | ||
329 | static inline u32 ram_userd_chan_size_v(void) | ||
330 | { | ||
331 | return 0x00000200; | ||
332 | } | ||
333 | static inline u32 ram_userd_put_w(void) | ||
334 | { | ||
335 | return 16; | ||
336 | } | ||
337 | static inline u32 ram_userd_get_w(void) | ||
338 | { | ||
339 | return 17; | ||
340 | } | ||
341 | static inline u32 ram_userd_ref_w(void) | ||
342 | { | ||
343 | return 18; | ||
344 | } | ||
345 | static inline u32 ram_userd_put_hi_w(void) | ||
346 | { | ||
347 | return 19; | ||
348 | } | ||
349 | static inline u32 ram_userd_ref_threshold_w(void) | ||
350 | { | ||
351 | return 20; | ||
352 | } | ||
353 | static inline u32 ram_userd_top_level_get_w(void) | ||
354 | { | ||
355 | return 22; | ||
356 | } | ||
357 | static inline u32 ram_userd_top_level_get_hi_w(void) | ||
358 | { | ||
359 | return 23; | ||
360 | } | ||
361 | static inline u32 ram_userd_get_hi_w(void) | ||
362 | { | ||
363 | return 24; | ||
364 | } | ||
365 | static inline u32 ram_userd_gp_get_w(void) | ||
366 | { | ||
367 | return 34; | ||
368 | } | ||
369 | static inline u32 ram_userd_gp_put_w(void) | ||
370 | { | ||
371 | return 35; | ||
372 | } | ||
373 | static inline u32 ram_userd_gp_top_level_get_w(void) | ||
374 | { | ||
375 | return 22; | ||
376 | } | ||
377 | static inline u32 ram_userd_gp_top_level_get_hi_w(void) | ||
378 | { | ||
379 | return 23; | ||
380 | } | ||
381 | static inline u32 ram_rl_entry_size_v(void) | ||
382 | { | ||
383 | return 0x00000008; | ||
384 | } | ||
385 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h new file mode 100644 index 00000000..3431116e --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h | |||
@@ -0,0 +1,225 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_therm_gm20b_h_ | ||
51 | #define _hw_therm_gm20b_h_ | ||
52 | |||
53 | static inline u32 therm_use_a_r(void) | ||
54 | { | ||
55 | return 0x00020798; | ||
56 | } | ||
57 | static inline u32 therm_evt_ext_therm_0_r(void) | ||
58 | { | ||
59 | return 0x00020700; | ||
60 | } | ||
61 | static inline u32 therm_evt_ext_therm_1_r(void) | ||
62 | { | ||
63 | return 0x00020704; | ||
64 | } | ||
65 | static inline u32 therm_evt_ext_therm_2_r(void) | ||
66 | { | ||
67 | return 0x00020708; | ||
68 | } | ||
69 | static inline u32 therm_evt_ba_w0_t1h_r(void) | ||
70 | { | ||
71 | return 0x00020750; | ||
72 | } | ||
73 | static inline u32 therm_weight_1_r(void) | ||
74 | { | ||
75 | return 0x00020024; | ||
76 | } | ||
77 | static inline u32 therm_peakpower_config1_r(u32 i) | ||
78 | { | ||
79 | return 0x00020154 + i*4; | ||
80 | } | ||
81 | static inline u32 therm_peakpower_config1_window_period_2m_v(void) | ||
82 | { | ||
83 | return 0x0000000f; | ||
84 | } | ||
85 | static inline u32 therm_peakpower_config1_window_period_2m_f(void) | ||
86 | { | ||
87 | return 0xf; | ||
88 | } | ||
89 | static inline u32 therm_peakpower_config1_window_en_enabled_f(void) | ||
90 | { | ||
91 | return 0x80000000; | ||
92 | } | ||
93 | static inline u32 therm_peakpower_config1_r(u32 i) | ||
94 | { | ||
95 | return 0x000202e8 + i*4; | ||
96 | } | ||
97 | static inline u32 therm_peakpower_config1_ba_sum_shift_s(void) | ||
98 | { | ||
99 | return 5; | ||
100 | } | ||
101 | static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v) | ||
102 | { | ||
103 | return (v & 0x1f) << 8; | ||
104 | } | ||
105 | static inline u32 therm_peakpower_config1_ba_sum_shift_m(void) | ||
106 | { | ||
107 | return 0x1f << 8; | ||
108 | } | ||
109 | static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r) | ||
110 | { | ||
111 | return (r >> 8) & 0x1f; | ||
112 | } | ||
113 | static inline u32 therm_peakpower_config2_r(u32 i) | ||
114 | { | ||
115 | return 0x00020170 + i*4; | ||
116 | } | ||
117 | static inline u32 therm_peakpower_config4_r(u32 i) | ||
118 | { | ||
119 | return 0x000201c0 + i*4; | ||
120 | } | ||
121 | static inline u32 therm_peakpower_config6_r(u32 i) | ||
122 | { | ||
123 | return 0x00020270 + i*4; | ||
124 | } | ||
125 | static inline u32 therm_peakpower_config8_r(u32 i) | ||
126 | { | ||
127 | return 0x000202e8 + i*4; | ||
128 | } | ||
129 | static inline u32 therm_peakpower_config9_r(u32 i) | ||
130 | { | ||
131 | return 0x000202f4 + i*4; | ||
132 | } | ||
133 | static inline u32 therm_config1_r(void) | ||
134 | { | ||
135 | return 0x00020050; | ||
136 | } | ||
137 | static inline u32 therm_gate_ctrl_r(u32 i) | ||
138 | { | ||
139 | return 0x00020200 + i*4; | ||
140 | } | ||
141 | static inline u32 therm_gate_ctrl_eng_clk_m(void) | ||
142 | { | ||
143 | return 0x3 << 0; | ||
144 | } | ||
145 | static inline u32 therm_gate_ctrl_eng_clk_run_f(void) | ||
146 | { | ||
147 | return 0x0; | ||
148 | } | ||
149 | static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) | ||
150 | { | ||
151 | return 0x1; | ||
152 | } | ||
153 | static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) | ||
154 | { | ||
155 | return 0x2; | ||
156 | } | ||
157 | static inline u32 therm_gate_ctrl_blk_clk_m(void) | ||
158 | { | ||
159 | return 0x3 << 2; | ||
160 | } | ||
161 | static inline u32 therm_gate_ctrl_blk_clk_run_f(void) | ||
162 | { | ||
163 | return 0x0; | ||
164 | } | ||
165 | static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) | ||
166 | { | ||
167 | return 0x4; | ||
168 | } | ||
169 | static inline u32 therm_gate_ctrl_eng_pwr_m(void) | ||
170 | { | ||
171 | return 0x3 << 4; | ||
172 | } | ||
173 | static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) | ||
174 | { | ||
175 | return 0x10; | ||
176 | } | ||
177 | static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) | ||
178 | { | ||
179 | return 0x00000002; | ||
180 | } | ||
181 | static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) | ||
182 | { | ||
183 | return 0x20; | ||
184 | } | ||
185 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) | ||
186 | { | ||
187 | return (v & 0x1f) << 8; | ||
188 | } | ||
189 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) | ||
190 | { | ||
191 | return 0x1f << 8; | ||
192 | } | ||
193 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) | ||
194 | { | ||
195 | return (v & 0x7) << 13; | ||
196 | } | ||
197 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) | ||
198 | { | ||
199 | return 0x7 << 13; | ||
200 | } | ||
201 | static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) | ||
202 | { | ||
203 | return (v & 0xf) << 20; | ||
204 | } | ||
205 | static inline u32 therm_gate_ctrl_eng_delay_after_m(void) | ||
206 | { | ||
207 | return 0xf << 20; | ||
208 | } | ||
209 | static inline u32 therm_fecs_idle_filter_r(void) | ||
210 | { | ||
211 | return 0x00020288; | ||
212 | } | ||
213 | static inline u32 therm_fecs_idle_filter_value_m(void) | ||
214 | { | ||
215 | return 0xffffffff << 0; | ||
216 | } | ||
217 | static inline u32 therm_hubmmu_idle_filter_r(void) | ||
218 | { | ||
219 | return 0x0002028c; | ||
220 | } | ||
221 | static inline u32 therm_hubmmu_idle_filter_value_m(void) | ||
222 | { | ||
223 | return 0xffffffff << 0; | ||
224 | } | ||
225 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_timer_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_timer_gm20b.h new file mode 100644 index 00000000..126f7c8c --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_timer_gm20b.h | |||
@@ -0,0 +1,101 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_timer_gm20b_h_ | ||
51 | #define _hw_timer_gm20b_h_ | ||
52 | |||
53 | static inline u32 timer_pri_timeout_r(void) | ||
54 | { | ||
55 | return 0x00009080; | ||
56 | } | ||
57 | static inline u32 timer_pri_timeout_period_f(u32 v) | ||
58 | { | ||
59 | return (v & 0xffffff) << 0; | ||
60 | } | ||
61 | static inline u32 timer_pri_timeout_period_m(void) | ||
62 | { | ||
63 | return 0xffffff << 0; | ||
64 | } | ||
65 | static inline u32 timer_pri_timeout_period_v(u32 r) | ||
66 | { | ||
67 | return (r >> 0) & 0xffffff; | ||
68 | } | ||
69 | static inline u32 timer_pri_timeout_en_f(u32 v) | ||
70 | { | ||
71 | return (v & 0x1) << 31; | ||
72 | } | ||
73 | static inline u32 timer_pri_timeout_en_m(void) | ||
74 | { | ||
75 | return 0x1 << 31; | ||
76 | } | ||
77 | static inline u32 timer_pri_timeout_en_v(u32 r) | ||
78 | { | ||
79 | return (r >> 31) & 0x1; | ||
80 | } | ||
81 | static inline u32 timer_pri_timeout_en_en_enabled_f(void) | ||
82 | { | ||
83 | return 0x80000000; | ||
84 | } | ||
85 | static inline u32 timer_pri_timeout_en_en_disabled_f(void) | ||
86 | { | ||
87 | return 0x0; | ||
88 | } | ||
89 | static inline u32 timer_pri_timeout_save_0_r(void) | ||
90 | { | ||
91 | return 0x00009084; | ||
92 | } | ||
93 | static inline u32 timer_pri_timeout_save_1_r(void) | ||
94 | { | ||
95 | return 0x00009088; | ||
96 | } | ||
97 | static inline u32 timer_pri_timeout_fecs_errcode_r(void) | ||
98 | { | ||
99 | return 0x0000908c; | ||
100 | } | ||
101 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h new file mode 100644 index 00000000..a2405a04 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h | |||
@@ -0,0 +1,137 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_top_gm20b_h_ | ||
51 | #define _hw_top_gm20b_h_ | ||
52 | |||
53 | static inline u32 top_num_gpcs_r(void) | ||
54 | { | ||
55 | return 0x00022430; | ||
56 | } | ||
57 | static inline u32 top_num_gpcs_value_v(u32 r) | ||
58 | { | ||
59 | return (r >> 0) & 0x1f; | ||
60 | } | ||
61 | static inline u32 top_tpc_per_gpc_r(void) | ||
62 | { | ||
63 | return 0x00022434; | ||
64 | } | ||
65 | static inline u32 top_tpc_per_gpc_value_v(u32 r) | ||
66 | { | ||
67 | return (r >> 0) & 0x1f; | ||
68 | } | ||
69 | static inline u32 top_num_fbps_r(void) | ||
70 | { | ||
71 | return 0x00022438; | ||
72 | } | ||
73 | static inline u32 top_num_fbps_value_v(u32 r) | ||
74 | { | ||
75 | return (r >> 0) & 0x1f; | ||
76 | } | ||
77 | static inline u32 top_num_ltcs_r(void) | ||
78 | { | ||
79 | return 0x00022454; | ||
80 | } | ||
81 | static inline u32 top_device_info_r(u32 i) | ||
82 | { | ||
83 | return 0x00022700 + i*4; | ||
84 | } | ||
85 | static inline u32 top_device_info__size_1_v(void) | ||
86 | { | ||
87 | return 0x00000040; | ||
88 | } | ||
89 | static inline u32 top_device_info_chain_v(u32 r) | ||
90 | { | ||
91 | return (r >> 31) & 0x1; | ||
92 | } | ||
93 | static inline u32 top_device_info_chain_enable_v(void) | ||
94 | { | ||
95 | return 0x00000001; | ||
96 | } | ||
97 | static inline u32 top_device_info_engine_enum_v(u32 r) | ||
98 | { | ||
99 | return (r >> 26) & 0xf; | ||
100 | } | ||
101 | static inline u32 top_device_info_runlist_enum_v(u32 r) | ||
102 | { | ||
103 | return (r >> 21) & 0xf; | ||
104 | } | ||
105 | static inline u32 top_device_info_type_enum_v(u32 r) | ||
106 | { | ||
107 | return (r >> 2) & 0x1fffffff; | ||
108 | } | ||
109 | static inline u32 top_device_info_type_enum_graphics_v(void) | ||
110 | { | ||
111 | return 0x00000000; | ||
112 | } | ||
113 | static inline u32 top_device_info_type_enum_graphics_f(void) | ||
114 | { | ||
115 | return 0x0; | ||
116 | } | ||
117 | static inline u32 top_device_info_type_enum_copy0_v(void) | ||
118 | { | ||
119 | return 0x00000001; | ||
120 | } | ||
121 | static inline u32 top_device_info_type_enum_copy0_f(void) | ||
122 | { | ||
123 | return 0x4; | ||
124 | } | ||
125 | static inline u32 top_device_info_entry_v(u32 r) | ||
126 | { | ||
127 | return (r >> 0) & 0x3; | ||
128 | } | ||
129 | static inline u32 top_device_info_entry_not_valid_v(void) | ||
130 | { | ||
131 | return 0x00000000; | ||
132 | } | ||
133 | static inline u32 top_device_info_entry_enum_v(void) | ||
134 | { | ||
135 | return 0x00000002; | ||
136 | } | ||
137 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h new file mode 100644 index 00000000..17f2af79 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h | |||
@@ -0,0 +1,289 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_trim_gm20b_h_ | ||
51 | #define _hw_trim_gm20b_h_ | ||
52 | |||
53 | static inline u32 trim_sys_gpcpll_cfg_r(void) | ||
54 | { | ||
55 | return 0x00137000; | ||
56 | } | ||
57 | static inline u32 trim_sys_gpcpll_cfg_enable_m(void) | ||
58 | { | ||
59 | return 0x1 << 0; | ||
60 | } | ||
61 | static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) | ||
62 | { | ||
63 | return (r >> 0) & 0x1; | ||
64 | } | ||
65 | static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) | ||
70 | { | ||
71 | return 0x1; | ||
72 | } | ||
73 | static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) | ||
74 | { | ||
75 | return 0x1 << 1; | ||
76 | } | ||
77 | static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) | ||
78 | { | ||
79 | return (r >> 1) & 0x1; | ||
80 | } | ||
81 | static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) | ||
82 | { | ||
83 | return 0x00000000; | ||
84 | } | ||
85 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) | ||
86 | { | ||
87 | return 0x1 << 4; | ||
88 | } | ||
89 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) | ||
90 | { | ||
91 | return 0x0; | ||
92 | } | ||
93 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) | ||
94 | { | ||
95 | return 0x10; | ||
96 | } | ||
97 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) | ||
98 | { | ||
99 | return (r >> 17) & 0x1; | ||
100 | } | ||
101 | static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) | ||
102 | { | ||
103 | return 0x20000; | ||
104 | } | ||
105 | static inline u32 trim_sys_gpcpll_coeff_r(void) | ||
106 | { | ||
107 | return 0x00137004; | ||
108 | } | ||
109 | static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) | ||
110 | { | ||
111 | return (v & 0xff) << 0; | ||
112 | } | ||
113 | static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) | ||
114 | { | ||
115 | return (r >> 0) & 0xff; | ||
116 | } | ||
117 | static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) | ||
118 | { | ||
119 | return (v & 0xff) << 8; | ||
120 | } | ||
121 | static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) | ||
122 | { | ||
123 | return 0xff << 8; | ||
124 | } | ||
125 | static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) | ||
126 | { | ||
127 | return (r >> 8) & 0xff; | ||
128 | } | ||
129 | static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) | ||
130 | { | ||
131 | return (v & 0x3f) << 16; | ||
132 | } | ||
133 | static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) | ||
134 | { | ||
135 | return (r >> 16) & 0x3f; | ||
136 | } | ||
137 | static inline u32 trim_sys_sel_vco_r(void) | ||
138 | { | ||
139 | return 0x00137100; | ||
140 | } | ||
141 | static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) | ||
142 | { | ||
143 | return 0x1 << 0; | ||
144 | } | ||
145 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) | ||
146 | { | ||
147 | return 0x00000000; | ||
148 | } | ||
149 | static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) | ||
150 | { | ||
151 | return 0x0; | ||
152 | } | ||
153 | static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) | ||
154 | { | ||
155 | return 0x0; | ||
156 | } | ||
157 | static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) | ||
158 | { | ||
159 | return 0x1; | ||
160 | } | ||
161 | static inline u32 trim_sys_gpc2clk_out_r(void) | ||
162 | { | ||
163 | return 0x00137250; | ||
164 | } | ||
165 | static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) | ||
166 | { | ||
167 | return 6; | ||
168 | } | ||
169 | static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) | ||
170 | { | ||
171 | return (v & 0x3f) << 0; | ||
172 | } | ||
173 | static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) | ||
174 | { | ||
175 | return 0x3f << 0; | ||
176 | } | ||
177 | static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) | ||
178 | { | ||
179 | return (r >> 0) & 0x3f; | ||
180 | } | ||
181 | static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) | ||
182 | { | ||
183 | return 0x3c; | ||
184 | } | ||
185 | static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) | ||
186 | { | ||
187 | return 0x3f << 8; | ||
188 | } | ||
189 | static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) | ||
190 | { | ||
191 | return 0x0; | ||
192 | } | ||
193 | static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) | ||
194 | { | ||
195 | return 0x1 << 31; | ||
196 | } | ||
197 | static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) | ||
198 | { | ||
199 | return 0x80000000; | ||
200 | } | ||
201 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) | ||
202 | { | ||
203 | return 0x00134124 + i*512; | ||
204 | } | ||
205 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) | ||
206 | { | ||
207 | return (v & 0x3fff) << 0; | ||
208 | } | ||
209 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) | ||
210 | { | ||
211 | return 0x10000; | ||
212 | } | ||
213 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) | ||
214 | { | ||
215 | return 0x100000; | ||
216 | } | ||
217 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) | ||
218 | { | ||
219 | return 0x1000000; | ||
220 | } | ||
221 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) | ||
222 | { | ||
223 | return 0x00134128 + i*512; | ||
224 | } | ||
225 | static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) | ||
226 | { | ||
227 | return (r >> 0) & 0xfffff; | ||
228 | } | ||
229 | static inline u32 trim_sys_gpcpll_cfg2_r(void) | ||
230 | { | ||
231 | return 0x0013700c; | ||
232 | } | ||
233 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) | ||
234 | { | ||
235 | return (v & 0xff) << 24; | ||
236 | } | ||
237 | static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) | ||
238 | { | ||
239 | return 0xff << 24; | ||
240 | } | ||
241 | static inline u32 trim_sys_gpcpll_cfg3_r(void) | ||
242 | { | ||
243 | return 0x00137018; | ||
244 | } | ||
245 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) | ||
246 | { | ||
247 | return (v & 0xff) << 16; | ||
248 | } | ||
249 | static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) | ||
250 | { | ||
251 | return 0xff << 16; | ||
252 | } | ||
253 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) | ||
254 | { | ||
255 | return 0x0013701c; | ||
256 | } | ||
257 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) | ||
258 | { | ||
259 | return 0x1 << 22; | ||
260 | } | ||
261 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) | ||
262 | { | ||
263 | return 0x400000; | ||
264 | } | ||
265 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) | ||
266 | { | ||
267 | return 0x0; | ||
268 | } | ||
269 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) | ||
270 | { | ||
271 | return 0x1 << 31; | ||
272 | } | ||
273 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) | ||
274 | { | ||
275 | return 0x80000000; | ||
276 | } | ||
277 | static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) | ||
278 | { | ||
279 | return 0x0; | ||
280 | } | ||
281 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) | ||
282 | { | ||
283 | return 0x001328a0; | ||
284 | } | ||
285 | static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) | ||
286 | { | ||
287 | return (r >> 24) & 0x1; | ||
288 | } | ||
289 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c new file mode 100644 index 00000000..134ac491 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -0,0 +1,197 @@ | |||
1 | /* | ||
2 | * GM20B L2 | ||
3 | * | ||
4 | * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | #include "hw_ltc_gm20b.h" | ||
19 | #include "hw_top_gm20b.h" | ||
20 | #include "hw_proj_gm20b.h" | ||
21 | #include "hw_pri_ringmaster_gm20b.h" | ||
22 | |||
23 | #include "gk20a/ltc_common.c" | ||
24 | #include "gk20a/gk20a.h" | ||
25 | #include "gk20a/gk20a_allocator.h" | ||
26 | |||
27 | static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | ||
28 | { | ||
29 | struct device *d = dev_from_gk20a(g); | ||
30 | DEFINE_DMA_ATTRS(attrs); | ||
31 | dma_addr_t iova; | ||
32 | |||
33 | /* max memory size (MB) to cover */ | ||
34 | u32 max_size = gr->max_comptag_mem; | ||
35 | /* one tag line covers 128KB */ | ||
36 | u32 max_comptag_lines = max_size << 3; | ||
37 | |||
38 | u32 hw_max_comptag_lines = | ||
39 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); | ||
40 | |||
41 | u32 cbc_param = | ||
42 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); | ||
43 | u32 comptags_per_cacheline = | ||
44 | ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); | ||
45 | u32 cacheline_size = | ||
46 | 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); | ||
47 | u32 slices_per_ltc = | ||
48 | ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); | ||
49 | |||
50 | u32 compbit_backing_size; | ||
51 | |||
52 | gk20a_dbg_fn(""); | ||
53 | |||
54 | if (max_comptag_lines == 0) { | ||
55 | gr->compbit_store.size = 0; | ||
56 | return 0; | ||
57 | } | ||
58 | |||
59 | if (max_comptag_lines > hw_max_comptag_lines) | ||
60 | max_comptag_lines = hw_max_comptag_lines; | ||
61 | |||
62 | /* no hybird fb */ | ||
63 | compbit_backing_size = | ||
64 | DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) * | ||
65 | cacheline_size * slices_per_ltc * gr->num_fbps; | ||
66 | |||
67 | /* aligned to 2KB * num_fbps */ | ||
68 | compbit_backing_size += | ||
69 | gr->num_fbps << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
70 | |||
71 | /* must be a multiple of 64KB */ | ||
72 | compbit_backing_size = roundup(compbit_backing_size, 64*1024); | ||
73 | |||
74 | max_comptag_lines = | ||
75 | (compbit_backing_size * comptags_per_cacheline) / | ||
76 | cacheline_size * slices_per_ltc * gr->num_fbps; | ||
77 | |||
78 | if (max_comptag_lines > hw_max_comptag_lines) | ||
79 | max_comptag_lines = hw_max_comptag_lines; | ||
80 | |||
81 | gk20a_dbg_info("compbit backing store size : %d", | ||
82 | compbit_backing_size); | ||
83 | gk20a_dbg_info("max comptag lines : %d", | ||
84 | max_comptag_lines); | ||
85 | |||
86 | dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs); | ||
87 | gr->compbit_store.size = compbit_backing_size; | ||
88 | gr->compbit_store.pages = dma_alloc_attrs(d, gr->compbit_store.size, | ||
89 | &iova, GFP_KERNEL, &attrs); | ||
90 | if (!gr->compbit_store.pages) { | ||
91 | gk20a_err(dev_from_gk20a(g), "failed to allocate" | ||
92 | "backing store for compbit : size %d", | ||
93 | compbit_backing_size); | ||
94 | return -ENOMEM; | ||
95 | } | ||
96 | gr->compbit_store.base_iova = iova; | ||
97 | |||
98 | gk20a_allocator_init(&gr->comp_tags, "comptag", | ||
99 | 1, /* start */ | ||
100 | max_comptag_lines - 1, /* length*/ | ||
101 | 1); /* align */ | ||
102 | |||
103 | return 0; | ||
104 | } | ||
105 | |||
106 | static int gm20b_ltc_clear_comptags(struct gk20a *g, u32 min, u32 max) | ||
107 | { | ||
108 | struct gr_gk20a *gr = &g->gr; | ||
109 | u32 fbp, slice, ctrl1, val; | ||
110 | unsigned long end_jiffies = jiffies + | ||
111 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
112 | u32 delay = GR_IDLE_CHECK_DEFAULT; | ||
113 | u32 slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v( | ||
114 | gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r())); | ||
115 | |||
116 | gk20a_dbg_fn(""); | ||
117 | |||
118 | if (gr->compbit_store.size == 0) | ||
119 | return 0; | ||
120 | |||
121 | gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl2_r(), | ||
122 | ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(min)); | ||
123 | gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl3_r(), | ||
124 | ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(max)); | ||
125 | gk20a_writel(g, ltc_ltcs_ltss_cbc_ctrl1_r(), | ||
126 | gk20a_readl(g, ltc_ltcs_ltss_cbc_ctrl1_r()) | | ||
127 | ltc_ltcs_ltss_cbc_ctrl1_clear_active_f()); | ||
128 | |||
129 | for (fbp = 0; fbp < gr->num_fbps; fbp++) { | ||
130 | for (slice = 0; slice < slices_per_ltc; slice++) { | ||
131 | |||
132 | delay = GR_IDLE_CHECK_DEFAULT; | ||
133 | |||
134 | ctrl1 = ltc_ltc0_lts0_cbc_ctrl1_r() + | ||
135 | fbp * proj_ltc_stride_v() + | ||
136 | slice * proj_lts_stride_v(); | ||
137 | |||
138 | do { | ||
139 | val = gk20a_readl(g, ctrl1); | ||
140 | if (ltc_ltcs_ltss_cbc_ctrl1_clear_v(val) != | ||
141 | ltc_ltcs_ltss_cbc_ctrl1_clear_active_v()) | ||
142 | break; | ||
143 | |||
144 | usleep_range(delay, delay * 2); | ||
145 | delay = min_t(u32, delay << 1, | ||
146 | GR_IDLE_CHECK_MAX); | ||
147 | |||
148 | } while (time_before(jiffies, end_jiffies) | | ||
149 | !tegra_platform_is_silicon()); | ||
150 | |||
151 | if (!time_before(jiffies, end_jiffies)) { | ||
152 | gk20a_err(dev_from_gk20a(g), | ||
153 | "comp tag clear timeout\n"); | ||
154 | return -EBUSY; | ||
155 | } | ||
156 | } | ||
157 | } | ||
158 | |||
159 | return 0; | ||
160 | } | ||
161 | |||
162 | static void gm20b_ltc_init_fs_state(struct gk20a *g) | ||
163 | { | ||
164 | gk20a_dbg_info("initialize gm20b l2"); | ||
165 | |||
166 | g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); | ||
167 | g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); | ||
168 | gk20a_dbg_info("%d ltcs out of %d", g->ltc_count, g->max_ltc_count); | ||
169 | |||
170 | gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), | ||
171 | g->ltc_count); | ||
172 | gk20a_writel(g, ltc_ltcs_misc_ltc_num_active_ltcs_r(), | ||
173 | g->ltc_count); | ||
174 | |||
175 | gk20a_writel(g, ltc_ltcs_ltss_dstg_cfg0_r(), | ||
176 | gk20a_readl(g, ltc_ltc0_lts0_dstg_cfg0_r()) | | ||
177 | ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m()); | ||
178 | } | ||
179 | |||
180 | void gm20b_init_ltc(struct gpu_ops *gops) | ||
181 | { | ||
182 | /* Gk20a reused ops. */ | ||
183 | gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes; | ||
184 | gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last; | ||
185 | gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; | ||
186 | gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; | ||
187 | gops->ltc.clear_zbc_color_entry = gk20a_ltc_clear_zbc_color_entry; | ||
188 | gops->ltc.clear_zbc_depth_entry = gk20a_ltc_clear_zbc_depth_entry; | ||
189 | gops->ltc.init_zbc = gk20a_ltc_init_zbc; | ||
190 | gops->ltc.init_cbc = gk20a_ltc_init_cbc; | ||
191 | |||
192 | /* GM20b specific ops. */ | ||
193 | gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; | ||
194 | gops->ltc.init_comptags = gm20b_ltc_init_comptags; | ||
195 | gops->ltc.clear_comptags = gm20b_ltc_clear_comptags; | ||
196 | gops->ltc.elpg_flush = gk20a_mm_g_elpg_flush_locked; | ||
197 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h new file mode 100644 index 00000000..c7524264 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * GM20B L2 | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVHOST_GM20B_LTC | ||
17 | #define _NVHOST_GM20B_LTC | ||
18 | struct gpu_ops; | ||
19 | |||
20 | void gm20b_init_ltc(struct gpu_ops *gops); | ||
21 | #endif | ||