diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-03-31 16:33:02 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-13 16:12:41 -0400 |
commit | 9b5427da37161c350d28a821652f2bb84bca360f (patch) | |
tree | 989e7b649b7b5e54d1d316b245b61c1881a15de6 /drivers/gpu/nvgpu/gm20b | |
parent | 2adf9164d9d68cc3ab700af84724034682f44ab8 (diff) |
gpu: nvgpu: Support GPUs with no physical mode
Support GPUs which cannot choose between SMMU and physical
addressing.
Change-Id: If3256fa1bc795a84d039ad3aa63ebdccf5cc0afb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1120469
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 16 |
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 79f90f0b..0e6e715d 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1169,7 +1169,7 @@ static int bl_bootstrap(struct pmu_gk20a *pmu, | |||
1169 | pwr_falcon_itfen_ctxen_enable_f()); | 1169 | pwr_falcon_itfen_ctxen_enable_f()); |
1170 | gk20a_writel(g, pwr_pmu_new_instblk_r(), | 1170 | gk20a_writel(g, pwr_pmu_new_instblk_r(), |
1171 | pwr_pmu_new_instblk_ptr_f( | 1171 | pwr_pmu_new_instblk_ptr_f( |
1172 | gk20a_mem_phys(&mm->pmu.inst_block) >> 12) | | 1172 | gk20a_mm_inst_block_addr(g, &mm->pmu.inst_block) >> 12) | |
1173 | pwr_pmu_new_instblk_valid_f(1) | | 1173 | pwr_pmu_new_instblk_valid_f(1) | |
1174 | pwr_pmu_new_instblk_target_sys_coh_f()); | 1174 | pwr_pmu_new_instblk_target_sys_coh_f()); |
1175 | 1175 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index b9763224..188d1781 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -20,25 +20,25 @@ | |||
20 | #include "hw_ram_gm20b.h" | 20 | #include "hw_ram_gm20b.h" |
21 | #include "hw_fifo_gm20b.h" | 21 | #include "hw_fifo_gm20b.h" |
22 | 22 | ||
23 | static void channel_gm20b_bind(struct channel_gk20a *ch_gk20a) | 23 | static void channel_gm20b_bind(struct channel_gk20a *c) |
24 | { | 24 | { |
25 | struct gk20a *g = ch_gk20a->g; | 25 | struct gk20a *g = c->g; |
26 | 26 | ||
27 | u32 inst_ptr = gk20a_mem_phys(&ch_gk20a->inst_block) | 27 | u32 inst_ptr = gk20a_mm_inst_block_addr(g, &c->inst_block) |
28 | >> ram_in_base_shift_v(); | 28 | >> ram_in_base_shift_v(); |
29 | 29 | ||
30 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", | 30 | gk20a_dbg_info("bind channel %d inst ptr 0x%08x", |
31 | ch_gk20a->hw_chid, inst_ptr); | 31 | c->hw_chid, inst_ptr); |
32 | 32 | ||
33 | ch_gk20a->bound = true; | 33 | c->bound = true; |
34 | 34 | ||
35 | gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid), | 35 | gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid), |
36 | ccsr_channel_inst_ptr_f(inst_ptr) | | 36 | ccsr_channel_inst_ptr_f(inst_ptr) | |
37 | ccsr_channel_inst_target_vid_mem_f() | | 37 | ccsr_channel_inst_target_vid_mem_f() | |
38 | ccsr_channel_inst_bind_true_f()); | 38 | ccsr_channel_inst_bind_true_f()); |
39 | 39 | ||
40 | gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid), | 40 | gk20a_writel(g, ccsr_channel_r(c->hw_chid), |
41 | (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) & | 41 | (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) & |
42 | ~ccsr_channel_enable_set_f(~0)) | | 42 | ~ccsr_channel_enable_set_f(~0)) | |
43 | ccsr_channel_enable_set_true_f()); | 43 | ccsr_channel_enable_set_true_f()); |
44 | } | 44 | } |