diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-03-09 17:10:00 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-16 12:17:22 -0400 |
commit | 95ef0315b99e32adbffc23bc8804a0127d3af10a (patch) | |
tree | d6e1dcfe05ceba5fc23bbb9d2aa6e5367c96a8f4 /drivers/gpu/nvgpu/gm20b | |
parent | 16ee09bb590d2c413d40a186743ecf003ac3c3d4 (diff) |
gpu: nvgpu: Use GPU's own fuse registers
Read fuse values from GPU's own fuse registers instead of Tegra fuse
registers whenever possible. This reduces the number of dependencies
to Linux fuse code.
Some fuses do not have a corresponding register in GPU, so they're
left as is.
Change-Id: Id9f2f4da897f3e20b20c300a67f705e3fa5ba35a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1318278
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index e036215f..d9fb2c53 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -14,8 +14,6 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/version.h> | ||
18 | #include <soc/tegra/fuse.h> | ||
19 | 17 | ||
20 | #include "gk20a/gk20a.h" | 18 | #include "gk20a/gk20a.h" |
21 | #include "gk20a/dbg_gpu_gk20a.h" | 19 | #include "gk20a/dbg_gpu_gk20a.h" |
@@ -39,10 +37,7 @@ | |||
39 | #include "therm_gm20b.h" | 37 | #include "therm_gm20b.h" |
40 | 38 | ||
41 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> | 39 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> |
42 | 40 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | |
43 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | ||
44 | #define FUSE_OPT_PRIV_SEC_DIS_0 0x264 | ||
45 | #endif | ||
46 | 41 | ||
47 | #define PRIV_SECURITY_DISABLE 0x01 | 42 | #define PRIV_SECURITY_DISABLE 0x01 |
48 | 43 | ||
@@ -197,8 +192,8 @@ int gm20b_init_hal(struct gk20a *g) | |||
197 | if (platform->is_fmodel) { | 192 | if (platform->is_fmodel) { |
198 | gops->privsecurity = 1; | 193 | gops->privsecurity = 1; |
199 | } else { | 194 | } else { |
200 | tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0, &val); | 195 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
201 | if (val & PRIV_SECURITY_DISABLE) { | 196 | if (!val) { |
202 | gk20a_dbg_info("priv security is disabled in HW"); | 197 | gk20a_dbg_info("priv security is disabled in HW"); |
203 | gops->privsecurity = 0; | 198 | gops->privsecurity = 0; |
204 | } else { | 199 | } else { |
@@ -210,8 +205,8 @@ int gm20b_init_hal(struct gk20a *g) | |||
210 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 205 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
211 | gops->privsecurity = 0; | 206 | gops->privsecurity = 0; |
212 | } else { | 207 | } else { |
213 | tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0, &val); | 208 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
214 | if (val & PRIV_SECURITY_DISABLE) { | 209 | if (!val) { |
215 | gops->privsecurity = 0; | 210 | gops->privsecurity = 0; |
216 | } else { | 211 | } else { |
217 | gk20a_dbg_info("priv security is not supported but enabled"); | 212 | gk20a_dbg_info("priv security is not supported but enabled"); |