diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-05-16 05:40:22 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-24 07:55:47 -0400 |
commit | 8f4a590cf22fa9691953e9be0dca18b399228167 (patch) | |
tree | e3a0e17ebba6116d0d72e0869a06507189bcfadf /drivers/gpu/nvgpu/gm20b | |
parent | 5570194dc4d97a857b354b706949e27663ebeee0 (diff) |
gpu: nvgpu: remove TEGRA_CLK_FRAMEWORK support
CONFIG_TEGRA_CLK_FRAMEWORK is no longer supported
hence remove this config and all the code that is
protected with this config
Jira NVGPU-49
Change-Id: Ica28019e0c99e95743216e005ba2fba20357b2d5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483090
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 106 |
1 files changed, 1 insertions, 105 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index d1dbf181..f1f75b74 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -22,7 +22,6 @@ | |||
22 | #include <linux/debugfs.h> | 22 | #include <linux/debugfs.h> |
23 | #include <linux/uaccess.h> | 23 | #include <linux/uaccess.h> |
24 | #endif | 24 | #endif |
25 | #include <linux/clk/tegra.h> | ||
26 | #include <soc/tegra/fuse.h> | 25 | #include <soc/tegra/fuse.h> |
27 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) | 26 | #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) |
28 | #include <soc/tegra/tegra-dvfs.h> | 27 | #include <soc/tegra/tegra-dvfs.h> |
@@ -1142,7 +1141,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1142 | { | 1141 | { |
1143 | struct clk_gk20a *clk = &g->clk; | 1142 | struct clk_gk20a *clk = &g->clk; |
1144 | unsigned long safe_rate; | 1143 | unsigned long safe_rate; |
1145 | struct clk *ref, *c; | 1144 | struct clk *ref = NULL, *c; |
1146 | int err; | 1145 | int err; |
1147 | 1146 | ||
1148 | gk20a_dbg_fn(""); | 1147 | gk20a_dbg_fn(""); |
@@ -1178,12 +1177,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1178 | */ | 1177 | */ |
1179 | c = clk_get_parent(clk->tegra_clk); | 1178 | c = clk_get_parent(clk->tegra_clk); |
1180 | 1179 | ||
1181 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1182 | ref = clk_get_parent(clk_get_parent(c)); | ||
1183 | #elif defined (CONFIG_COMMON_CLK) | ||
1184 | ref = clk_get_sys("gpu_ref", "gpu_ref"); | 1180 | ref = clk_get_sys("gpu_ref", "gpu_ref"); |
1185 | #endif | ||
1186 | |||
1187 | if (IS_ERR(ref)) { | 1181 | if (IS_ERR(ref)) { |
1188 | nvgpu_err(g, "failed to get GPCPLL reference clock"); | 1182 | nvgpu_err(g, "failed to get GPCPLL reference clock"); |
1189 | err = -EINVAL; | 1183 | err = -EINVAL; |
@@ -1474,91 +1468,6 @@ static int set_pll_freq(struct gk20a *g, int allow_slide) | |||
1474 | return err; | 1468 | return err; |
1475 | } | 1469 | } |
1476 | 1470 | ||
1477 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1478 | static int gm20b_clk_export_set_rate(void *data, unsigned long *rate) | ||
1479 | { | ||
1480 | u32 old_freq; | ||
1481 | int ret = -ENODATA; | ||
1482 | struct gk20a *g = data; | ||
1483 | struct clk_gk20a *clk = &g->clk; | ||
1484 | |||
1485 | if (rate) { | ||
1486 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1487 | old_freq = clk->gpc_pll.freq; | ||
1488 | ret = set_pll_target(g, rate_gpu_to_gpc2clk(*rate), old_freq); | ||
1489 | if (!ret && clk->gpc_pll.enabled && clk->clk_hw_on) | ||
1490 | ret = set_pll_freq(g, 1); | ||
1491 | if (!ret) | ||
1492 | *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
1493 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1494 | } | ||
1495 | return ret; | ||
1496 | } | ||
1497 | |||
1498 | static int gm20b_clk_export_enable(void *data) | ||
1499 | { | ||
1500 | int ret = 0; | ||
1501 | struct gk20a *g = data; | ||
1502 | struct clk_gk20a *clk = &g->clk; | ||
1503 | |||
1504 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1505 | if (!clk->gpc_pll.enabled && clk->clk_hw_on) | ||
1506 | ret = set_pll_freq(g, 1); | ||
1507 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1508 | return ret; | ||
1509 | } | ||
1510 | |||
1511 | static void gm20b_clk_export_disable(void *data) | ||
1512 | { | ||
1513 | struct gk20a *g = data; | ||
1514 | struct clk_gk20a *clk = &g->clk; | ||
1515 | |||
1516 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1517 | if (clk->gpc_pll.enabled && clk->clk_hw_on) | ||
1518 | clk_disable_gpcpll(g, 1); | ||
1519 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1520 | } | ||
1521 | |||
1522 | static void gm20b_clk_export_init(void *data, unsigned long *rate, bool *state) | ||
1523 | { | ||
1524 | struct gk20a *g = data; | ||
1525 | struct clk_gk20a *clk = &g->clk; | ||
1526 | |||
1527 | nvgpu_mutex_acquire(&clk->clk_mutex); | ||
1528 | if (state) | ||
1529 | *state = clk->gpc_pll.enabled; | ||
1530 | if (rate) | ||
1531 | *rate = rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
1532 | nvgpu_mutex_release(&clk->clk_mutex); | ||
1533 | } | ||
1534 | |||
1535 | static struct tegra_clk_export_ops gm20b_clk_export_ops = { | ||
1536 | .init = gm20b_clk_export_init, | ||
1537 | .enable = gm20b_clk_export_enable, | ||
1538 | .disable = gm20b_clk_export_disable, | ||
1539 | .set_rate = gm20b_clk_export_set_rate, | ||
1540 | }; | ||
1541 | |||
1542 | static int gm20b_clk_register_export_ops(struct gk20a *g) | ||
1543 | { | ||
1544 | int ret; | ||
1545 | struct clk *c; | ||
1546 | |||
1547 | if (gm20b_clk_export_ops.data) | ||
1548 | return 0; | ||
1549 | |||
1550 | gm20b_clk_export_ops.data = (void *)g; | ||
1551 | c = g->clk.tegra_clk; | ||
1552 | if (!c || !clk_get_parent(c)) | ||
1553 | return -ENOSYS; | ||
1554 | |||
1555 | ret = tegra_clk_register_export_ops(clk_get_parent(c), | ||
1556 | &gm20b_clk_export_ops); | ||
1557 | |||
1558 | return ret; | ||
1559 | } | ||
1560 | #endif /* CONFIG_TEGRA_CLK_FRAMEWORK */ | ||
1561 | |||
1562 | static int gm20b_init_clk_support(struct gk20a *g) | 1471 | static int gm20b_init_clk_support(struct gk20a *g) |
1563 | { | 1472 | { |
1564 | struct clk_gk20a *clk = &g->clk; | 1473 | struct clk_gk20a *clk = &g->clk; |
@@ -1570,13 +1479,6 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1570 | if (err) | 1479 | if (err) |
1571 | return err; | 1480 | return err; |
1572 | 1481 | ||
1573 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1574 | clk->g = g; | ||
1575 | err = gm20b_init_clk_setup_sw(g); | ||
1576 | if (err) | ||
1577 | return err; | ||
1578 | #endif | ||
1579 | |||
1580 | nvgpu_mutex_acquire(&clk->clk_mutex); | 1482 | nvgpu_mutex_acquire(&clk->clk_mutex); |
1581 | clk->clk_hw_on = true; | 1483 | clk->clk_hw_on = true; |
1582 | 1484 | ||
@@ -1585,12 +1487,6 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1585 | if (err) | 1487 | if (err) |
1586 | return err; | 1488 | return err; |
1587 | 1489 | ||
1588 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1589 | err = gm20b_clk_register_export_ops(g); | ||
1590 | if (err) | ||
1591 | return err; | ||
1592 | #endif | ||
1593 | |||
1594 | /* FIXME: this effectively prevents host level clock gating */ | 1490 | /* FIXME: this effectively prevents host level clock gating */ |
1595 | err = clk_prepare_enable(g->clk.tegra_clk); | 1491 | err = clk_prepare_enable(g->clk.tegra_clk); |
1596 | if (err) | 1492 | if (err) |