diff options
author | Richard Zhao <rizhao@nvidia.com> | 2015-11-16 19:30:28 -0500 |
---|---|---|
committer | Vladislav Buzov <vbuzov@nvidia.com> | 2015-11-23 13:20:54 -0500 |
commit | 8ec63298789a0912b9cbd90ee47c76f0701f0dca (patch) | |
tree | 34f8ba228b78dfde64ffc3badb86338aeb1159b2 /drivers/gpu/nvgpu/gm20b | |
parent | 7f79d647d6f8beffc5d98d3b703f9408b5a05d14 (diff) |
gpu: nvgpu: correct register setting for debug mode
correct register settings for both set mmu debug mode and
set sm debug mode.
JIRA VFND-1005
Bug 1594604
Change-Id: I1d4b1d4b4cdd9d24d3b00481e0e22c4217f5a4b3
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/833490
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vladislav Buzov <vbuzov@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 24 |
2 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h index 214306cb..5ec4a46e 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_fb_gm20b.h | |||
@@ -222,10 +222,18 @@ static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) | |||
222 | { | 222 | { |
223 | return 0x00000001; | 223 | return 0x00000001; |
224 | } | 224 | } |
225 | static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void) | ||
226 | { | ||
227 | return 0x10000; | ||
228 | } | ||
225 | static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) | 229 | static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) |
226 | { | 230 | { |
227 | return 0x00000000; | 231 | return 0x00000000; |
228 | } | 232 | } |
233 | static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) | ||
234 | { | ||
235 | return 0x0; | ||
236 | } | ||
229 | static inline u32 fb_mmu_vpr_info_r(void) | 237 | static inline u32 fb_mmu_vpr_info_r(void) |
230 | { | 238 | { |
231 | return 0x00100cd0; | 239 | return 0x00100cd0; |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index d91d40af..a941eb59 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -3070,6 +3070,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) | |||
3070 | { | 3070 | { |
3071 | return 0x00504610; | 3071 | return 0x00504610; |
3072 | } | 3072 | } |
3073 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) | ||
3074 | { | ||
3075 | return 0x1 << 0; | ||
3076 | } | ||
3073 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) | 3077 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) |
3074 | { | 3078 | { |
3075 | return (r >> 0) & 0x1; | 3079 | return (r >> 0) & 0x1; |
@@ -3078,6 +3082,18 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) | |||
3078 | { | 3082 | { |
3079 | return 0x00000001; | 3083 | return 0x00000001; |
3080 | } | 3084 | } |
3085 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_f(void) | ||
3086 | { | ||
3087 | return 0x1; | ||
3088 | } | ||
3089 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) | ||
3090 | { | ||
3091 | return 0x00000000; | ||
3092 | } | ||
3093 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_f(void) | ||
3094 | { | ||
3095 | return 0x0; | ||
3096 | } | ||
3081 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | 3097 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) |
3082 | { | 3098 | { |
3083 | return 0x80000000; | 3099 | return 0x80000000; |
@@ -3090,6 +3106,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | |||
3090 | { | 3106 | { |
3091 | return 0x40000000; | 3107 | return 0x40000000; |
3092 | } | 3108 | } |
3109 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) | ||
3110 | { | ||
3111 | return 0x1 << 1; | ||
3112 | } | ||
3093 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) | 3113 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) |
3094 | { | 3114 | { |
3095 | return (r >> 1) & 0x1; | 3115 | return (r >> 1) & 0x1; |
@@ -3098,6 +3118,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) | |||
3098 | { | 3118 | { |
3099 | return 0x0; | 3119 | return 0x0; |
3100 | } | 3120 | } |
3121 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) | ||
3122 | { | ||
3123 | return 0x1 << 2; | ||
3124 | } | ||
3101 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) | 3125 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) |
3102 | { | 3126 | { |
3103 | return (r >> 2) & 0x1; | 3127 | return (r >> 2) & 0x1; |