diff options
author | Sam Payne <spayne@nvidia.com> | 2014-10-31 17:27:33 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:56 -0400 |
commit | 8c6a9fd1151299697037d58f33cfa306d8ac5d87 (patch) | |
tree | 9bb909474f12565e7f61251b8b80f300030bde52 /drivers/gpu/nvgpu/gm20b | |
parent | 4f6dddcf78233b9939ee32c6f09519f27c3b8fb4 (diff) |
Revert "gpu: nvgpu: GR and LTC HAL to use const structs"
This reverts commit 41b82e97164138f45fbdaef6ab6939d82ca9419e.
Change-Id: Iabd01fcb124e0d22cd9be62151a6552cbb27fc94
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/592221
Tested-by: Hoang Pham <hopham@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 91 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h | 79 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 38 |
4 files changed, 72 insertions, 144 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 7b69c5c8..8a3de4e8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPU GR | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
@@ -16,7 +16,6 @@ | |||
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/delay.h> /* for mdelay */ | 17 | #include <linux/delay.h> /* for mdelay */ |
18 | 18 | ||
19 | #include "gr_ops.h" | ||
20 | #include "gk20a/gk20a.h" | 19 | #include "gk20a/gk20a.h" |
21 | #include "gk20a/gr_gk20a.h" | 20 | #include "gk20a/gr_gk20a.h" |
22 | 21 | ||
@@ -29,7 +28,7 @@ | |||
29 | #include "pmu_gm20b.h" | 28 | #include "pmu_gm20b.h" |
30 | #include "acr_gm20b.h" | 29 | #include "acr_gm20b.h" |
31 | 30 | ||
32 | void gr_gm20b_init_gpc_mmu(struct gk20a *g) | 31 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) |
33 | { | 32 | { |
34 | u32 temp; | 33 | u32 temp; |
35 | 34 | ||
@@ -65,7 +64,7 @@ void gr_gm20b_init_gpc_mmu(struct gk20a *g) | |||
65 | gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); | 64 | gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); |
66 | } | 65 | } |
67 | 66 | ||
68 | void gr_gm20b_bundle_cb_defaults(struct gk20a *g) | 67 | static void gr_gm20b_bundle_cb_defaults(struct gk20a *g) |
69 | { | 68 | { |
70 | struct gr_gk20a *gr = &g->gr; | 69 | struct gr_gk20a *gr = &g->gr; |
71 | 70 | ||
@@ -77,7 +76,7 @@ void gr_gm20b_bundle_cb_defaults(struct gk20a *g) | |||
77 | gr_pd_ab_dist_cfg2_token_limit_init_v(); | 76 | gr_pd_ab_dist_cfg2_token_limit_init_v(); |
78 | } | 77 | } |
79 | 78 | ||
80 | void gr_gm20b_cb_size_default(struct gk20a *g) | 79 | static void gr_gm20b_cb_size_default(struct gk20a *g) |
81 | { | 80 | { |
82 | struct gr_gk20a *gr = &g->gr; | 81 | struct gr_gk20a *gr = &g->gr; |
83 | 82 | ||
@@ -87,7 +86,7 @@ void gr_gm20b_cb_size_default(struct gk20a *g) | |||
87 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); | 86 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); |
88 | } | 87 | } |
89 | 88 | ||
90 | int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) | 89 | static int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) |
91 | { | 90 | { |
92 | struct gr_gk20a *gr = &g->gr; | 91 | struct gr_gk20a *gr = &g->gr; |
93 | int size; | 92 | int size; |
@@ -108,7 +107,7 @@ int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) | |||
108 | return size; | 107 | return size; |
109 | } | 108 | } |
110 | 109 | ||
111 | void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, | 110 | static void gr_gk20a_commit_global_attrib_cb(struct gk20a *g, |
112 | struct channel_ctx_gk20a *ch_ctx, | 111 | struct channel_ctx_gk20a *ch_ctx, |
113 | u64 addr, bool patch) | 112 | u64 addr, bool patch) |
114 | { | 113 | { |
@@ -125,7 +124,7 @@ void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, | |||
125 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); | 124 | gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); |
126 | } | 125 | } |
127 | 126 | ||
128 | void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, | 127 | static void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, |
129 | struct channel_ctx_gk20a *ch_ctx, | 128 | struct channel_ctx_gk20a *ch_ctx, |
130 | u64 addr, u64 size, bool patch) | 129 | u64 addr, u64 size, bool patch) |
131 | { | 130 | { |
@@ -161,7 +160,7 @@ void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, | |||
161 | 160 | ||
162 | } | 161 | } |
163 | 162 | ||
164 | int gr_gm20b_commit_global_cb_manager(struct gk20a *g, | 163 | static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, |
165 | struct channel_gk20a *c, bool patch) | 164 | struct channel_gk20a *c, bool patch) |
166 | { | 165 | { |
167 | struct gr_gk20a *gr = &g->gr; | 166 | struct gr_gk20a *gr = &g->gr; |
@@ -248,7 +247,7 @@ int gr_gm20b_commit_global_cb_manager(struct gk20a *g, | |||
248 | return 0; | 247 | return 0; |
249 | } | 248 | } |
250 | 249 | ||
251 | void gr_gm20b_commit_global_pagepool(struct gk20a *g, | 250 | static void gr_gm20b_commit_global_pagepool(struct gk20a *g, |
252 | struct channel_ctx_gk20a *ch_ctx, | 251 | struct channel_ctx_gk20a *ch_ctx, |
253 | u64 addr, u32 size, bool patch) | 252 | u64 addr, u32 size, bool patch) |
254 | { | 253 | { |
@@ -260,7 +259,7 @@ void gr_gm20b_commit_global_pagepool(struct gk20a *g, | |||
260 | 259 | ||
261 | } | 260 | } |
262 | 261 | ||
263 | int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, | 262 | static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, |
264 | u32 class_num, u32 offset, u32 data) | 263 | u32 class_num, u32 offset, u32 data) |
265 | { | 264 | { |
266 | gk20a_dbg_fn(""); | 265 | gk20a_dbg_fn(""); |
@@ -281,10 +280,10 @@ int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, | |||
281 | gk20a_gr_set_shader_exceptions(g, data); | 280 | gk20a_gr_set_shader_exceptions(g, data); |
282 | break; | 281 | break; |
283 | case NVB197_SET_CIRCULAR_BUFFER_SIZE: | 282 | case NVB197_SET_CIRCULAR_BUFFER_SIZE: |
284 | g->ops.gr->set_circular_buffer_size(g, data); | 283 | g->ops.gr.set_circular_buffer_size(g, data); |
285 | break; | 284 | break; |
286 | case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE: | 285 | case NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE: |
287 | g->ops.gr->set_alpha_circular_buffer_size(g, data); | 286 | g->ops.gr.set_alpha_circular_buffer_size(g, data); |
288 | break; | 287 | break; |
289 | default: | 288 | default: |
290 | goto fail; | 289 | goto fail; |
@@ -296,7 +295,7 @@ fail: | |||
296 | return -EINVAL; | 295 | return -EINVAL; |
297 | } | 296 | } |
298 | 297 | ||
299 | void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) | 298 | static void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) |
300 | { | 299 | { |
301 | struct gr_gk20a *gr = &g->gr; | 300 | struct gr_gk20a *gr = &g->gr; |
302 | u32 gpc_index, ppc_index, stride, val; | 301 | u32 gpc_index, ppc_index, stride, val; |
@@ -396,7 +395,7 @@ void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data) | |||
396 | } | 395 | } |
397 | } | 396 | } |
398 | 397 | ||
399 | void gr_gm20b_enable_hww_exceptions(struct gk20a *g) | 398 | static void gr_gm20b_enable_hww_exceptions(struct gk20a *g) |
400 | { | 399 | { |
401 | gr_gk20a_enable_hww_exceptions(g); | 400 | gr_gk20a_enable_hww_exceptions(g); |
402 | 401 | ||
@@ -407,7 +406,7 @@ void gr_gm20b_enable_hww_exceptions(struct gk20a *g) | |||
407 | gr_ds_hww_report_mask_2_sph24_err_report_f()); | 406 | gr_ds_hww_report_mask_2_sph24_err_report_f()); |
408 | } | 407 | } |
409 | 408 | ||
410 | void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) | 409 | static void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) |
411 | { | 410 | { |
412 | /* setup sm warp esr report masks */ | 411 | /* setup sm warp esr report masks */ |
413 | gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(), | 412 | gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(), |
@@ -440,7 +439,7 @@ void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) | |||
440 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()); | 439 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()); |
441 | } | 440 | } |
442 | 441 | ||
443 | bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) | 442 | static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) |
444 | { | 443 | { |
445 | bool valid = false; | 444 | bool valid = false; |
446 | 445 | ||
@@ -460,7 +459,7 @@ bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) | |||
460 | return valid; | 459 | return valid; |
461 | } | 460 | } |
462 | 461 | ||
463 | void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, | 462 | static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, |
464 | u32 *num_sm_dsm_perf_regs, | 463 | u32 *num_sm_dsm_perf_regs, |
465 | u32 **sm_dsm_perf_regs, | 464 | u32 **sm_dsm_perf_regs, |
466 | u32 *perf_register_stride) | 465 | u32 *perf_register_stride) |
@@ -471,7 +470,7 @@ void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, | |||
471 | *perf_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); | 470 | *perf_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); |
472 | } | 471 | } |
473 | 472 | ||
474 | void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | 473 | static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, |
475 | u32 *num_sm_dsm_perf_regs, | 474 | u32 *num_sm_dsm_perf_regs, |
476 | u32 **sm_dsm_perf_regs, | 475 | u32 **sm_dsm_perf_regs, |
477 | u32 *ctrl_register_stride) | 476 | u32 *ctrl_register_stride) |
@@ -482,7 +481,7 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | |||
482 | *ctrl_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); | 481 | *ctrl_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); |
483 | } | 482 | } |
484 | 483 | ||
485 | u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 484 | static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
486 | { | 485 | { |
487 | u32 val; | 486 | u32 val; |
488 | struct gr_gk20a *gr = &g->gr; | 487 | struct gr_gk20a *gr = &g->gr; |
@@ -493,7 +492,7 @@ u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
493 | return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); | 492 | return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); |
494 | } | 493 | } |
495 | 494 | ||
496 | int gr_gm20b_init_fs_state(struct gk20a *g) | 495 | static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g) |
497 | { | 496 | { |
498 | struct gr_gk20a *gr = &g->gr; | 497 | struct gr_gk20a *gr = &g->gr; |
499 | u32 tpc_index, gpc_index; | 498 | u32 tpc_index, gpc_index; |
@@ -596,7 +595,7 @@ int gr_gm20b_init_fs_state(struct gk20a *g) | |||
596 | return 0; | 595 | return 0; |
597 | } | 596 | } |
598 | 597 | ||
599 | int gr_gm20b_falcon_load_ucode(struct gk20a *g, u64 addr_base, | 598 | static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, |
600 | struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset) | 599 | struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset) |
601 | { | 600 | { |
602 | gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(), | 601 | gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(), |
@@ -623,7 +622,7 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) | |||
623 | 622 | ||
624 | gr_gk20a_load_falcon_bind_instblk(g); | 623 | gr_gk20a_load_falcon_bind_instblk(g); |
625 | 624 | ||
626 | g->ops.gr->falcon_load_ucode(g, addr_base, | 625 | g->ops.gr.falcon_load_ucode(g, addr_base, |
627 | &g->ctxsw_ucode_info.gpccs, | 626 | &g->ctxsw_ucode_info.gpccs, |
628 | gr_gpcs_gpccs_falcon_hwcfg_r() - | 627 | gr_gpcs_gpccs_falcon_hwcfg_r() - |
629 | gr_fecs_falcon_hwcfg_r()); | 628 | gr_fecs_falcon_hwcfg_r()); |
@@ -649,7 +648,7 @@ static int gr_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout, u32 val) | |||
649 | return -ETIMEDOUT; | 648 | return -ETIMEDOUT; |
650 | } | 649 | } |
651 | 650 | ||
652 | int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | 651 | static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) |
653 | { | 652 | { |
654 | u32 err; | 653 | u32 err; |
655 | gk20a_dbg_fn(""); | 654 | gk20a_dbg_fn(""); |
@@ -711,30 +710,42 @@ int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
711 | } | 710 | } |
712 | #else | 711 | #else |
713 | 712 | ||
714 | int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | 713 | static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) |
715 | { | 714 | { |
716 | return -EPERM; | 715 | return -EPERM; |
717 | } | 716 | } |
718 | 717 | ||
719 | #endif | 718 | #endif |
720 | 719 | ||
721 | #include "gk20a/gr_ops_gk20a.h" | ||
722 | #include "gr_ops_gm20b.h" | ||
723 | |||
724 | static struct gpu_gr_ops gm20b_gr_ops = { | ||
725 | __set_gr_gm20b_ops(), | ||
726 | __set_gr_gk20a_op(load_ctxsw_ucode) | ||
727 | }; | ||
728 | |||
729 | static struct gpu_gr_ops gm20b_gr_privsecurity_ops = { | ||
730 | __set_gr_gm20b_ops(), | ||
731 | __set_gr_gm20b_op(load_ctxsw_ucode) | ||
732 | }; | ||
733 | |||
734 | void gm20b_init_gr(struct gpu_ops *gops) | 720 | void gm20b_init_gr(struct gpu_ops *gops) |
735 | { | 721 | { |
722 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | ||
723 | gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; | ||
724 | gops->gr.cb_size_default = gr_gm20b_cb_size_default; | ||
725 | gops->gr.calc_global_ctx_buffer_size = | ||
726 | gr_gm20b_calc_global_ctx_buffer_size; | ||
727 | gops->gr.commit_global_attrib_cb = gr_gk20a_commit_global_attrib_cb; | ||
728 | gops->gr.commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb; | ||
729 | gops->gr.commit_global_cb_manager = gr_gm20b_commit_global_cb_manager; | ||
730 | gops->gr.commit_global_pagepool = gr_gm20b_commit_global_pagepool; | ||
731 | gops->gr.handle_sw_method = gr_gm20b_handle_sw_method; | ||
732 | gops->gr.set_alpha_circular_buffer_size = gr_gm20b_set_alpha_circular_buffer_size; | ||
733 | gops->gr.set_circular_buffer_size = gr_gm20b_set_circular_buffer_size; | ||
734 | gops->gr.enable_hww_exceptions = gr_gm20b_enable_hww_exceptions; | ||
735 | gops->gr.is_valid_class = gr_gm20b_is_valid_class; | ||
736 | gops->gr.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs; | ||
737 | gops->gr.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs; | ||
738 | gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep; | ||
739 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; | ||
740 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; | ||
736 | if (gops->privsecurity) | 741 | if (gops->privsecurity) |
737 | gops->gr = &gm20b_gr_privsecurity_ops; | 742 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; |
738 | else | 743 | else |
739 | gops->gr = &gm20b_gr_ops; | 744 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; |
745 | gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask; | ||
746 | gops->gr.free_channel_ctx = gk20a_free_channel_ctx; | ||
747 | gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; | ||
748 | gops->gr.free_obj_ctx = gk20a_free_obj_ctx; | ||
749 | gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; | ||
750 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; | ||
740 | } | 751 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index e822b33c..8348b9d9 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPU GR | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
@@ -13,8 +13,8 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #ifndef _NVGPU_GR_GM20B_H_ | 16 | #ifndef _NVHOST_GM20B_GR_MMU_H |
17 | #define _NVGPU_GR_GM20B_H_ | 17 | #define _NVHOST_GM20B_GR_MMU_H |
18 | struct gk20a; | 18 | struct gk20a; |
19 | 19 | ||
20 | enum { | 20 | enum { |
@@ -29,7 +29,5 @@ enum { | |||
29 | #define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 | 29 | #define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 |
30 | 30 | ||
31 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 31 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
32 | |||
33 | struct gpu_ops; | ||
34 | void gm20b_init_gr(struct gpu_ops *gops); | 32 | void gm20b_init_gr(struct gpu_ops *gops); |
35 | #endif | 33 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h deleted file mode 100644 index 9477da75..00000000 --- a/drivers/gpu/nvgpu/gm20b/gr_ops_gm20b.h +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | /* | ||
2 | * GM20B GPU graphics ops | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _GR_OPS_GM20B_H_ | ||
17 | #define _GR_OPS_GM20B_H_ | ||
18 | |||
19 | #include "gr_ops.h" | ||
20 | |||
21 | #define __gr_gm20b_op(X) gr_gm20b_ ## X | ||
22 | #define __set_gr_gm20b_op(X) . X = gr_gm20b_ ## X | ||
23 | |||
24 | void __gr_gm20b_op(init_gpc_mmu)(struct gk20a *); | ||
25 | void __gr_gm20b_op(bundle_cb_defaults)(struct gk20a *); | ||
26 | void __gr_gm20b_op(cb_size_default)(struct gk20a *); | ||
27 | int __gr_gm20b_op(calc_global_ctx_buffer_size)(struct gk20a *); | ||
28 | void __gr_gm20b_op(commit_global_bundle_cb)(struct gk20a *, | ||
29 | struct channel_ctx_gk20a *, u64, u64, bool); | ||
30 | int __gr_gm20b_op(commit_global_cb_manager)(struct gk20a *, | ||
31 | struct channel_gk20a *, bool); | ||
32 | void __gr_gm20b_op(commit_global_pagepool)(struct gk20a *, | ||
33 | struct channel_ctx_gk20a *, u64 , u32, bool); | ||
34 | int __gr_gm20b_op(handle_sw_method)(struct gk20a *, u32 , u32, u32, u32); | ||
35 | void __gr_gm20b_op(set_alpha_circular_buffer_size)(struct gk20a *, u32); | ||
36 | void __gr_gm20b_op(set_circular_buffer_size)(struct gk20a *, u32); | ||
37 | void __gr_gm20b_op(enable_hww_exceptions)(struct gk20a *); | ||
38 | bool __gr_gm20b_op(is_valid_class)(struct gk20a *, u32); | ||
39 | void __gr_gm20b_op(get_sm_dsm_perf_regs)(struct gk20a *, u32 *, u32 **, u32 *); | ||
40 | void __gr_gm20b_op(get_sm_dsm_perf_ctrl_regs)(struct gk20a *, | ||
41 | u32 *, u32 **, u32 *); | ||
42 | int __gr_gm20b_op(init_fs_state)(struct gk20a *); | ||
43 | void __gr_gm20b_op(set_hww_esr_report_mask)(struct gk20a *); | ||
44 | int __gr_gm20b_op(falcon_load_ucode)(struct gk20a *, | ||
45 | u64, struct gk20a_ctxsw_ucode_segments *, u32); | ||
46 | u32 __gr_gm20b_op(get_gpc_tpc_mask)(struct gk20a *, u32); | ||
47 | int __gr_gm20b_op(load_ctxsw_ucode)(struct gk20a *); | ||
48 | |||
49 | #define __set_gr_gm20b_ops() \ | ||
50 | /* newly defined for gm20b */ \ | ||
51 | __set_gr_gm20b_op(init_gpc_mmu), \ | ||
52 | __set_gr_gm20b_op(bundle_cb_defaults), \ | ||
53 | __set_gr_gm20b_op(cb_size_default), \ | ||
54 | __set_gr_gm20b_op(calc_global_ctx_buffer_size), \ | ||
55 | __set_gr_gm20b_op(commit_global_bundle_cb), \ | ||
56 | __set_gr_gm20b_op(commit_global_cb_manager), \ | ||
57 | __set_gr_gm20b_op(commit_global_pagepool), \ | ||
58 | __set_gr_gm20b_op(handle_sw_method), \ | ||
59 | __set_gr_gm20b_op(set_alpha_circular_buffer_size), \ | ||
60 | __set_gr_gm20b_op(set_circular_buffer_size), \ | ||
61 | __set_gr_gm20b_op(enable_hww_exceptions), \ | ||
62 | __set_gr_gm20b_op(is_valid_class), \ | ||
63 | __set_gr_gm20b_op(get_sm_dsm_perf_regs), \ | ||
64 | __set_gr_gm20b_op(get_sm_dsm_perf_ctrl_regs), \ | ||
65 | __set_gr_gm20b_op(init_fs_state), \ | ||
66 | __set_gr_gm20b_op(set_hww_esr_report_mask), \ | ||
67 | __set_gr_gm20b_op(falcon_load_ucode), \ | ||
68 | __set_gr_gm20b_op(get_gpc_tpc_mask), \ | ||
69 | \ | ||
70 | /* reused from gk20a */ \ | ||
71 | __set_gr_gk20a_op(access_smpc_reg), \ | ||
72 | __set_gr_gk20a_op(commit_global_attrib_cb), \ | ||
73 | __set_gr_gk20a_op(free_channel_ctx), \ | ||
74 | __set_gr_gk20a_op(alloc_obj_ctx), \ | ||
75 | __set_gr_gk20a_op(free_obj_ctx), \ | ||
76 | __set_gr_gk20a_op(bind_ctxsw_zcull), \ | ||
77 | __set_gr_gk20a_op(get_zcull_info) | ||
78 | |||
79 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 2a888e88..a089b59c 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -388,26 +388,24 @@ static int gm20b_determine_L2_size_bytes(struct gk20a *g) | |||
388 | return cache_size; | 388 | return cache_size; |
389 | } | 389 | } |
390 | 390 | ||
391 | static struct gpu_ltc_ops gm20b_ltc_ops = { | ||
392 | .determine_L2_size_bytes = gm20b_determine_L2_size_bytes, | ||
393 | .set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last, | ||
394 | .set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry, | ||
395 | .set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry, | ||
396 | .init_cbc = gk20a_ltc_init_cbc, | ||
397 | #ifdef CONFIG_DEBUG_FS | ||
398 | .sync_debugfs = gk20a_ltc_sync_debugfs, | ||
399 | #endif | ||
400 | /* GM20b specific ops. */ | ||
401 | .init_fs_state = gm20b_ltc_init_fs_state, | ||
402 | .init_comptags = gm20b_ltc_init_comptags, | ||
403 | .cbc_ctrl = gm20b_ltc_cbc_ctrl, | ||
404 | .elpg_flush = gm20b_ltc_g_elpg_flush_locked, | ||
405 | .isr = gm20b_ltc_isr, | ||
406 | .cbc_fix_config = gm20b_ltc_cbc_fix_config, | ||
407 | .flush = gm20b_flush_ltc | ||
408 | }; | ||
409 | |||
410 | void gm20b_init_ltc(struct gpu_ops *gops) | 391 | void gm20b_init_ltc(struct gpu_ops *gops) |
411 | { | 392 | { |
412 | gops->ltc = &gm20b_ltc_ops; | 393 | /* Gk20a reused ops. */ |
394 | gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes; | ||
395 | gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last; | ||
396 | gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; | ||
397 | gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; | ||
398 | gops->ltc.init_cbc = gk20a_ltc_init_cbc; | ||
399 | |||
400 | /* GM20b specific ops. */ | ||
401 | gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; | ||
402 | gops->ltc.init_comptags = gm20b_ltc_init_comptags; | ||
403 | gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; | ||
404 | gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; | ||
405 | gops->ltc.isr = gm20b_ltc_isr; | ||
406 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; | ||
407 | gops->ltc.flush = gm20b_flush_ltc; | ||
408 | #ifdef CONFIG_DEBUG_FS | ||
409 | gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; | ||
410 | #endif | ||
413 | } | 411 | } |