gpu: nvgpu: PMU init sequence change

-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
 method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
 for PMU RTOS & does start PMU RTOS in secure & non-secure
 based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
 falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
 secured_pmu_start assignment for gp106 & gv100 to support
 modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
 files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
 to handle non secure PMU bootstrap, reused this method
 for need chips.

JIRA NVGPU-1146

Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 80 insertions, 75 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index a4657ff3..e38e9a85 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1045,76 +1045,6 @@ int acr_ucode_patch_sig(struct gk20a *g,
         return 0;
 }
 
-int gm20b_init_nspmu_setup_hw1(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err = 0;
-
-        nvgpu_log_fn(g, " ");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        err = g->ops.pmu.pmu_nsbootstrap(pmu);
-
-        return err;
-}
-
-void gm20b_setup_apertures(struct gk20a *g)
-{
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                        pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-}
-
-void gm20b_update_lspmu_cmdline_args(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        /*Copying pmu cmdline args*/
-        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
-                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
-        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
-                pmu, GK20A_PMU_TRACE_BUFSIZE);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
-                pmu, GK20A_PMU_DMAIDX_VIRT);
-        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
-                (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
-                g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
-}
-
 static int nvgpu_gm20b_acr_wait_for_completion(struct gk20a *g,
         struct nvgpu_falcon *flcn, unsigned int timeout)
 {
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index cae6ab6a..fad40081 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -41,10 +41,6 @@ int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
         void *lsfm, u32 *p_bl_gen_desc_size);
 int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
         void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
-void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
-void gm20b_setup_apertures(struct gk20a *g);
-int gm20b_pmu_setup_sw(struct gk20a *g);
-int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
 
 int acr_ucode_patch_sig(struct gk20a *g,
                 unsigned int *p_img,
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 52f86dab..133428da 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -735,7 +735,8 @@ int gm20b_init_hal(struct gk20a *g)
                         gm20b_flcn_populate_bl_dmem_desc;
                 gops->pmu.update_lspmu_cmdline_args =
                         gm20b_update_lspmu_cmdline_args;
-                gops->pmu.setup_apertures = gm20b_setup_apertures;
+                gops->pmu.setup_apertures = gm20b_pmu_setup_apertures;
+                gops->pmu.secured_pmu_start = gm20b_secured_pmu_start;
 
                 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
                 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
@@ -745,6 +746,8 @@ int gm20b_init_hal(struct gk20a *g)
                 /* Inherit from gk20a */
                 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
                 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
+                gops->pmu.pmu_setup_hw_and_bootstrap =
+                        gm20b_ns_pmu_setup_hw_and_bootstrap;
                 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
 
                 gops->pmu.load_lsfalcon_ucode = NULL;
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 6e764ac5..df0ae58d 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -278,6 +278,72 @@ bool gm20b_pmu_is_debug_mode_en(struct gk20a *g)
         return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U;
 }
 
+int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g)
+{
+        struct nvgpu_pmu *pmu = &g->pmu;
+
+        nvgpu_log_fn(g, " ");
+
+        nvgpu_mutex_acquire(&pmu->isr_mutex);
+        nvgpu_flcn_reset(pmu->flcn);
+        pmu->isr_enabled = true;
+        nvgpu_mutex_release(&pmu->isr_mutex);
+
+        /* setup apertures - virtual */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+                pwr_fbif_transcfg_mem_type_virtual_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+                pwr_fbif_transcfg_mem_type_virtual_f());
+        /* setup apertures - physical */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+                pwr_fbif_transcfg_mem_type_physical_f() |
+                pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+                pwr_fbif_transcfg_mem_type_physical_f() |
+                pwr_fbif_transcfg_target_coherent_sysmem_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+                pwr_fbif_transcfg_mem_type_physical_f() |
+                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+
+        return g->ops.pmu.pmu_nsbootstrap(pmu);
+}
+
+void gm20b_pmu_setup_apertures(struct gk20a *g)
+{
+        /* setup apertures - virtual */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
+                        pwr_fbif_transcfg_mem_type_virtual_f());
+        /* setup apertures - physical */
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_local_fb_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_coherent_sysmem_f());
+        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
+                        pwr_fbif_transcfg_mem_type_physical_f() |
+                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
+}
+
+void gm20b_update_lspmu_cmdline_args(struct gk20a *g)
+{
+        struct nvgpu_pmu *pmu = &g->pmu;
+        /*Copying pmu cmdline args*/
+        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
+                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
+        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
+                pmu, GK20A_PMU_TRACE_BUFSIZE);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
+        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
+                pmu, GK20A_PMU_DMAIDX_VIRT);
+        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
+                (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
+                g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
+}
 
 static int gm20b_bl_bootstrap(struct gk20a *g,
         struct nvgpu_falcon_bl_info *bl_info)
@@ -337,3 +403,9 @@ int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g,
 exit:
         return err;
 }
+
+void gm20b_secured_pmu_start(struct gk20a *g)
+{
+        gk20a_writel(g, pwr_falcon_cpuctl_alias_r(),
+                pwr_falcon_cpuctl_startcpu_f(1));
+}
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
index 37634783..0e4968fb 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
@@ -34,7 +34,11 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags);
 int gm20b_pmu_init_acr(struct gk20a *g);
 void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);
 bool gm20b_pmu_is_debug_mode_en(struct gk20a *g);
+int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g);
+void gm20b_pmu_setup_apertures(struct gk20a *g);
+void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
 int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g,
         struct hs_acr *acr_desc,
         struct nvgpu_falcon_bl_info *bl_info);
+void gm20b_secured_pmu_start(struct gk20a *g);
 #endif /*NVGPU_GM20B_PMU_GM20B_H*/