diff options
author | Vijayakumar <vsubbu@nvidia.com> | 2014-09-30 10:49:44 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:52 -0400 |
commit | 748475df20bbe6843bdf4fbc02384dc5aa28866e (patch) | |
tree | 700012cf758d6731017b8b23153abae4311bf065 /drivers/gpu/nvgpu/gm20b | |
parent | 4739499f07b29282ee1031d08adaa76c238da2a6 (diff) |
gpu: nvgpu: gm20b: Support secure FECS recovery
When falcons are secured use PMU commands to reload
FECS firmware.
Bug 200042729
Change-Id: I09f2472b16dac6a510dba067bce3950075973d5f
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/552544
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 69 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 96 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 1 |
3 files changed, 158 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 660ffa88..8a3de4e8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -14,6 +14,7 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/delay.h> /* for mdelay */ | ||
17 | 18 | ||
18 | #include "gk20a/gk20a.h" | 19 | #include "gk20a/gk20a.h" |
19 | #include "gk20a/gr_gk20a.h" | 20 | #include "gk20a/gr_gk20a.h" |
@@ -24,6 +25,8 @@ | |||
24 | #include "hw_proj_gm20b.h" | 25 | #include "hw_proj_gm20b.h" |
25 | #include "hw_ctxsw_prog_gm20b.h" | 26 | #include "hw_ctxsw_prog_gm20b.h" |
26 | #include "hw_fuse_gm20b.h" | 27 | #include "hw_fuse_gm20b.h" |
28 | #include "pmu_gm20b.h" | ||
29 | #include "acr_gm20b.h" | ||
27 | 30 | ||
28 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | 31 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) |
29 | { | 32 | { |
@@ -625,8 +628,29 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) | |||
625 | gr_fecs_falcon_hwcfg_r()); | 628 | gr_fecs_falcon_hwcfg_r()); |
626 | } | 629 | } |
627 | 630 | ||
631 | static int gr_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout, u32 val) | ||
632 | { | ||
633 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); | ||
634 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; | ||
635 | u32 reg; | ||
636 | |||
637 | gk20a_dbg_fn(""); | ||
638 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); | ||
639 | do { | ||
640 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); | ||
641 | if (reg == val) | ||
642 | return 0; | ||
643 | usleep_range(delay, delay * 2); | ||
644 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | ||
645 | } while (time_before(jiffies, end_jiffies) || | ||
646 | !tegra_platform_is_silicon()); | ||
647 | |||
648 | return -ETIMEDOUT; | ||
649 | } | ||
650 | |||
628 | static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | 651 | static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) |
629 | { | 652 | { |
653 | u32 err; | ||
630 | gk20a_dbg_fn(""); | 654 | gk20a_dbg_fn(""); |
631 | 655 | ||
632 | if (tegra_platform_is_linsim()) { | 656 | if (tegra_platform_is_linsim()) { |
@@ -636,16 +660,49 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
636 | gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777)); | 660 | gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777)); |
637 | } | 661 | } |
638 | 662 | ||
663 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), ~0x0); | ||
664 | gm20b_pmu_load_lsf(g, LSF_FALCON_ID_FECS); | ||
665 | |||
639 | gr_gm20b_load_gpccs_with_bootloader(g); | 666 | gr_gm20b_load_gpccs_with_bootloader(g); |
640 | 667 | ||
641 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0x0); | 668 | if (g->ops.pmu.fecsrecoveryinprogress) { |
642 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1); | 669 | unsigned long timeout = gk20a_get_gr_idle_timeout(g); |
643 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(6), 0xffffffff); | 670 | err = gr_gm20b_ctx_wait_lsf_ready(g, timeout, 0x55AA55AA); |
671 | if (err) { | ||
672 | gk20a_err(dev_from_gk20a(g), "Unable to recover FECS"); | ||
673 | return err; | ||
674 | } else { | ||
675 | g->ops.pmu.fecsrecoveryinprogress = 0; | ||
676 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), ~0x0); | ||
677 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1); | ||
678 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(6), | ||
679 | 0xffffffff); | ||
680 | |||
681 | gk20a_writel(g, gr_gpccs_dmactl_r(), | ||
682 | gr_gpccs_dmactl_require_ctx_f(0)); | ||
683 | gk20a_writel(g, gr_gpccs_cpuctl_r(), | ||
684 | gr_gpccs_cpuctl_startcpu_f(1)); | ||
685 | |||
686 | gk20a_writel(g, gr_fecs_cpuctl_alias_r(), | ||
687 | gr_fecs_cpuctl_startcpu_f(1)); | ||
688 | } | ||
689 | } | ||
644 | 690 | ||
645 | gk20a_writel(g, gr_gpccs_dmactl_r(), gr_gpccs_dmactl_require_ctx_f(0)); | ||
646 | 691 | ||
647 | gk20a_writel(g, gr_gpccs_cpuctl_r(), gr_gpccs_cpuctl_startcpu_f(1)); | 692 | if (!g->ops.pmu.fecsbootstrapdone) { |
648 | gk20a_writel(g, gr_fecs_cpuctl_alias_r(), gr_fecs_cpuctl_startcpu_f(1)); | 693 | g->ops.pmu.fecsbootstrapdone = true; |
694 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), ~0x0); | ||
695 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1); | ||
696 | gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(6), 0xffffffff); | ||
697 | |||
698 | gk20a_writel(g, gr_gpccs_dmactl_r(), | ||
699 | gr_gpccs_dmactl_require_ctx_f(0)); | ||
700 | gk20a_writel(g, gr_gpccs_cpuctl_r(), | ||
701 | gr_gpccs_cpuctl_startcpu_f(1)); | ||
702 | |||
703 | gk20a_writel(g, gr_fecs_cpuctl_alias_r(), | ||
704 | gr_fecs_cpuctl_startcpu_f(1)); | ||
705 | } | ||
649 | 706 | ||
650 | gk20a_dbg_fn("done"); | 707 | gk20a_dbg_fn("done"); |
651 | 708 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 98dc6845..91927950 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -13,7 +13,9 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/delay.h> /* for udelay */ | ||
16 | #include "gk20a/gk20a.h" | 17 | #include "gk20a/gk20a.h" |
18 | #include "gk20a/pmu_gk20a.h" | ||
17 | #include "acr_gm20b.h" | 19 | #include "acr_gm20b.h" |
18 | #include "pmu_gm20b.h" | 20 | #include "pmu_gm20b.h" |
19 | 21 | ||
@@ -26,6 +28,9 @@ struct pg_init_sequence_list { | |||
26 | u32 writeval; | 28 | u32 writeval; |
27 | }; | 29 | }; |
28 | 30 | ||
31 | #define gm20b_dbg_pmu(fmt, arg...) \ | ||
32 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | ||
33 | |||
29 | 34 | ||
30 | /* PROD settings for ELPG sequencing registers*/ | 35 | /* PROD settings for ELPG sequencing registers*/ |
31 | static struct pg_init_sequence_list _pginitseq_gm20b[] = { | 36 | static struct pg_init_sequence_list _pginitseq_gm20b[] = { |
@@ -148,11 +153,98 @@ int gm20b_pmu_setup_elpg(struct gk20a *g) | |||
148 | return ret; | 153 | return ret; |
149 | } | 154 | } |
150 | 155 | ||
156 | void pmu_handle_acr_init_wpr_msg(struct gk20a *g, struct pmu_msg *msg, | ||
157 | void *param, u32 handle, u32 status) | ||
158 | { | ||
159 | gk20a_dbg_fn(""); | ||
160 | |||
161 | gm20b_dbg_pmu("reply PMU_ACR_CMD_ID_INIT_WPR_REGION"); | ||
162 | |||
163 | if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) | ||
164 | g->ops.pmu.lspmuwprinitdone = true; | ||
165 | gk20a_dbg_fn("done"); | ||
166 | } | ||
167 | |||
168 | |||
169 | int gm20b_pmu_init_acr(struct gk20a *g) | ||
170 | { | ||
171 | struct pmu_gk20a *pmu = &g->pmu; | ||
172 | struct pmu_cmd cmd; | ||
173 | u32 seq; | ||
174 | |||
175 | gk20a_dbg_fn(""); | ||
176 | |||
177 | /* init ACR */ | ||
178 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
179 | cmd.hdr.unit_id = PMU_UNIT_ACR; | ||
180 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
181 | sizeof(struct pmu_acr_cmd_init_wpr_details); | ||
182 | cmd.cmd.acr.init_wpr.cmd_type = PMU_ACR_CMD_ID_INIT_WPR_REGION; | ||
183 | cmd.cmd.acr.init_wpr.regionid = 0x01; | ||
184 | cmd.cmd.acr.init_wpr.wproffset = 0x00; | ||
185 | gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION"); | ||
186 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
187 | pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0); | ||
188 | |||
189 | gk20a_dbg_fn("done"); | ||
190 | return 0; | ||
191 | } | ||
192 | |||
193 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | ||
194 | void *param, u32 handle, u32 status) | ||
195 | { | ||
196 | |||
197 | gk20a_dbg_fn(""); | ||
198 | |||
199 | |||
200 | if (msg->msg.acr.acrmsg.falconid == LSF_FALCON_ID_FECS) | ||
201 | gm20b_dbg_pmu("reply PMU_ACR_CMD_ID_BOOTSTRAP_FALCON"); | ||
202 | |||
203 | gm20b_dbg_pmu("response code = %x\n", msg->msg.acr.acrmsg.falconid); | ||
204 | gk20a_dbg_fn("done"); | ||
205 | } | ||
206 | |||
207 | void gm20b_pmu_load_lsf(struct gk20a *g, u8 falcon_id) | ||
208 | { | ||
209 | struct pmu_gk20a *pmu = &g->pmu; | ||
210 | struct pmu_cmd cmd; | ||
211 | u32 seq; | ||
212 | |||
213 | gk20a_dbg_fn(""); | ||
214 | |||
215 | gm20b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); | ||
216 | if (g->ops.pmu.lspmuwprinitdone && g->ops.pmu.fecsbootstrapdone) { | ||
217 | /* send message to load FECS falcon */ | ||
218 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
219 | cmd.hdr.unit_id = PMU_UNIT_ACR; | ||
220 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
221 | sizeof(struct pmu_acr_cmd_bootstrap_falcon); | ||
222 | cmd.cmd.acr.bootstrap_falcon.cmd_type = | ||
223 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON; | ||
224 | cmd.cmd.acr.bootstrap_falcon.flags = | ||
225 | PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | ||
226 | cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id; | ||
227 | gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON"); | ||
228 | g->ops.pmu.fecsrecoveryinprogress = 1; | ||
229 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
230 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | ||
231 | } | ||
232 | |||
233 | gk20a_dbg_fn("done"); | ||
234 | return; | ||
235 | } | ||
236 | |||
151 | void gm20b_init_pmu_ops(struct gpu_ops *gops) | 237 | void gm20b_init_pmu_ops(struct gpu_ops *gops) |
152 | { | 238 | { |
153 | if (gops->privsecurity) | 239 | if (gops->privsecurity) { |
154 | gm20b_init_secure_pmu(gops); | 240 | gm20b_init_secure_pmu(gops); |
155 | else | 241 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
242 | } else { | ||
156 | gk20a_init_pmu_ops(gops); | 243 | gk20a_init_pmu_ops(gops); |
244 | gops->pmu.init_wpr_region = NULL; | ||
245 | } | ||
157 | gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg; | 246 | gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg; |
247 | gops->pmu.lspmuwprinitdone = false; | ||
248 | gops->pmu.fecsbootstrapdone = false; | ||
249 | gops->pmu.fecsrecoveryinprogress = 0; | ||
158 | } | 250 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index fc2f7d60..f62a0786 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | |||
@@ -17,5 +17,6 @@ | |||
17 | #define __PMU_GM20B_H_ | 17 | #define __PMU_GM20B_H_ |
18 | 18 | ||
19 | void gm20b_init_pmu_ops(struct gpu_ops *gops); | 19 | void gm20b_init_pmu_ops(struct gpu_ops *gops); |
20 | void gm20b_pmu_load_lsf(struct gk20a *g, u8 falcon_id); | ||
20 | 21 | ||
21 | #endif /*__PMU_GM20B_H_*/ | 22 | #endif /*__PMU_GM20B_H_*/ |