gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox size

fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug

Bug 2093809

Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698026
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 9fc3a494..76837ab7 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -324,6 +324,7 @@ static const struct gpu_ops gm20b_ops = {
                 .get_pmm_per_chiplet_offset =
                         gr_gm20b_get_pmm_per_chiplet_offset,
                 .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+                .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
         },
         .fb = {
                 .reset = fb_gk20a_reset,